参数资料
| 型号： | ISL6269IRZ |
| 厂商： | Intersil |
| 文件页数： | 7/14页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 16-QFN |
| 标准包装： | 75 |
| 系列： | Robust Ripple Regulator™ (R³) |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 600kHz |
| 电源电压： | 7 V ~ 25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 16-VQFN 裸露焊盘 |
| 包装： | 管件 |
ISL6269
LG (Pin 11)
The LG pin is the output of the low-side MOSFET gate
measures the VIN and VO pin voltages. The positive slope
of V R can be written as:
driver. Connect to the gate of the low-side MOSFET.
PVCC (Pin 12)
The PVCC pin is the input voltage bias for the LG low-side
MOSFET gate driver. Connect +5V from the PVCC pin to the
V RPOS = ( g m ) ? ( V IN – V OUT )
The negative slope of V R can be written as:
V RNEG = g m ? V OUT
(EQ. 1)
(EQ. 2)
PGND pin. Decouple with at least 1μF of an MLCC capacitor
across the PVCC and PGND pins. The VCC output may be
used for the PVCC input voltage source.
BOOT (Pin 13)
The BOOT pin stores the input voltage for the UG high-side
MOSFET gate driver. Connect an MLCC capacitor across
the BOOT and PHASE pins. The boot capacitor is charged
through an internal boot diode connected from the PVCC pin
to the BOOT pin, each time the PHASE pin drops below
PVCC minus the voltage dropped across the internal boot
diode.
UG (Pin 14)
The UG pin is the output of the high-side MOSFET gate
driver. Connect to the gate of the high-side MOSFET.
Where g m is the gain of the transconductance amplifier.
A window voltage V W is referenced with respect to the error
amplifier output voltage V COMP , creating an envelope into
which the ripple voltage V R is compared. The amplitude of
V W is set by a resistor connected across the FSET and GND
pins. The V R, V COMP, and V W signals feed into a window
comparator in which V COMP is the lower threshold voltage
and V W is the higher threshold voltage. Figure 3 shows
PWM pulses being generated as V R traverses the V W and
V COMP thresholds . The PWM switching frequency is
proportional to the slew rates of the positive and negative
slopes of V R; the PWM switching frequency is inversely
proportional to the voltage between V W and V COMP.
PHASE (Pin 15)
The PHASE pin detects the voltage polarity of the PHASE
node and is also the current return path for the UG high-side
MOSFET gate driver. Connect the PHASE pin to the node
consisting of the high-side MOSFET source, the low-side
MOSFET drain, and the output inductor.
PGOOD (Pin 16)
The PGOOD pin is an open-drain output that indicates when
the converter is able to supply regulated voltage. Connect
the PGOOD pin to +5V through a pull-up resistor.
GND (Bottom Pad)
Ripple Capacitor Voltage CR
Window Voltage VW
Error Amplifier Voltage VCOMP
PWM
Signal common of the IC. Unless otherwise stated, signals
are referenced to the GND pin, not the PGND pin.
Theory of Operation
Modulator
The ISL6269 is a hybrid of fixed frequency PWM control, and
variable frequency hysteretic control. Intersil’s R 3 technology
can simultaneously affect the PWM switching frequency and
PWM duty cycle in response to input voltage and output load
transients. The term “Ripple” in the name “Robust-Ripple-
Regulator” refers to the converter output inductor ripple
current, not the converter output ripple voltage. The R 3
modulator synthesizes an AC signal V R , which is an ideal
representation of the output inductor ripple current. The
duty-cycle of V R is the result of charge and discharge
current through a ripple capacitor C R . The current through
C R is provided by a transconductance amplifier g m that
7
FIGURE 3. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
EN, LDO, and POR
The VCC LDO regulates by pulling up towards the voltage at
the VIN pin; the LDO has no pull-down capability. The LDO
is enabled when the EN pin surpasses the rising EN threshold
voltage V ENTHR . The ISL6269 is enabled once V VCC has
increased above the rising power-on reset (POR) V VCC_THR
threshold voltage. The controller immediately stops
generating PWM and disables the LDO when the EN pin is
pulled below the falling EN threshold voltage V ENTHF . The IC
completely shuts off when V VCC decreases below the falling
POR V VCC_THF threshold voltage.
Soft-Start, and PGOOD
The ISL6269 uses a digital soft-start circuit to ramp the
output voltage of the converter to the programmed regulation
setpoint at a predictable slew rate. The slew rate of the
soft-start sequence has been selected to limit the inrush
current through the output capacitors as they charge to the
FN9177.3
June 25, 2009
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| ISL6269IRZ-T | 功能描述:IC REG CTRLR BUCK PWM 16-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:Robust Ripple Regulator™ (R³) 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6271A | 制造商:INTERSIL 制造商全称:Intersil Corporation 功能描述:Integrated XScale Regulator |
| ISL6271ACR | 功能描述:IC REG PMIC 1BUCK 2LDO 20-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 电源管理 - 专用 系列:- 应用说明:Ultrasound Imaging Systems Application Note 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:37 系列:- 应用:医疗用超声波成像，声纳 电流 - 电源:- 电源电压:2.37 V ~ 6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:56-WFQFN 裸露焊盘 供应商设备封装:56-TQFN-EP（8x8） 包装:管件 |
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| ISL6271ACRZ | 功能描述:直流/直流开关调节器 LD PLL & SRAMG FOR I NTEL PROCESSORS IBM RoHS:否 制造商:International Rectifier 最大输入电压:21 V 开关频率:1.5 MHz 输出电压:0.5 V to 0.86 V 输出电流:4 A 输出端数量: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:PQFN 4 x 5 |
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