参数资料
型号: ISL62871HRUZ-T
厂商: Intersil
文件页数: 13/25页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 16-TQFN
标准包装: 3,000
系列: Robust Ripple Regulator™ (R³)
PWM 型: 控制器
输出数: 1
频率 - 最大: 330kHz
占空比: 100%
电源电压: 3.3 V ~ 25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -10°C ~ 100°C
封装/外壳: 16-UFQFN
包装: 带卷 (TR)
ISL62871, ISL62872
External Setpoint Reference
The IC can use an external setpoint reference voltage as an
alternative to VID-selected, resistor-programmed setpoints.
This is accomplished by removing all setpoint programming
resistors, connecting the SET0 pin to the VCC pin, and
feeding the external setpoint reference voltage to the VID0
pin. When SET0 and VCC are tied together, the following
internal reconfigurations take place:
- VID0 pin opens its 500nA pull-down current sink
- Reference source selector switch SW4 moves from INT
position (internal 500mV) to EXT position (VID0 pin)
- VID1 pin is disabled
The converter will now be in regulation when the voltage on
the FB pin equals the voltage on the VID0 pin. As with
resistor-programmed setpoints, the reference voltage range
on the VID0 pin is 500mV to 1.5V. Use Equations 1, 2, and 3
beginning on page 11 should it become necessary to
implement an output voltage-divider network to make the
external setpoint reference voltage compatible with the
Where:
- I SS is the soft-start current source at the 20μA limit
- V START-UP is the setpoint reference voltage selected by
the state of the VID inputs at the time EN is asserted
- R T is the sum of the R SET programming resistors
The end of soft-start is detected by I SS tapering off when
capacitor C SOFT charges to the designated V SET voltage
reference setpoint. The SSOK flag is set, the PGOOD pin
goes high, and the I SS current source changes over to the
voltage-step current source I VS which has a current limit of
±100μA. Whenever the VID inputs or the external setpoint
reference, programs a different setpoint reference voltage,
the I VS current source charges or discharges capacitor
C SOFT to that new level at ±100μA. Once C SOFT charges to
the selected setpoint voltage, the I VS current source comes
out of the 100μA current limit and decays to the static value
set by V SREF ÷ R T . The elapsed time to charge C SOFT to
the new voltage is called the voltage-step delay t VS and is
given by Equation 19:
t VS = ( I VS ? C SOFT ) ? LN ( 1 – ------------------------------------------- )
I ? R
500mV to 1.5V constraint.
Soft-Start and Voltage-Step Delay
( V NEW – V OLD )
VS T
(EQ. 19)
C SOFT = ---------------------------------------------------------------------
I SS ? R T
? R T ? LN ( 1 – ------------------------------ ) ?
t SS is the soft-start delay
V START-UP is the setpoint reference voltage selected by
Circuit Description
When the voltage on the VCC pin has ramped above the
rising power-on reset voltage V VCC_THR , and the voltage on
the EN pin has increased above the rising enable threshold
voltage V ENTHR , the SREF pin releases its discharge clamp
and enables the reference amplifier V SET . The soft-start
current I SS is limited to 20μA and is sourced out of the SREF
pin into the parallel RC network of capacitor C SOFT and
resistance R T . The resistance R T is the sum of all the series
connected R SET programming resistors and is written as
Equation 17:
R T = R SET1 + R SET2 + … R SET ( n ) (EQ. 17)
The voltage on the SREF pin rises as I SS charges C SOFT to
the voltage reference setpoint selected by the state of the
VID inputs at the time the EN pin is asserted. The regulator
controls the PWM such that the voltage on the FB pin tracks
the rising voltage on the SREF pin. Once C SOFT charges to
the selected setpoint voltage, the I SS current source comes
out of the 20μA current limit and decays to the static value
set by V SREF ÷ R T . The elapsed time from when the EN pin
is asserted to when V SREF has reached the voltage
reference setpoint is the soft-start delay t SS which is given
by Equation 18:
Where:
- I VS is the ±100μA setpoint voltage-step current
- V NEW is the new setpoint voltage selected by the VID
inputs
- V OLD is the setpoint voltage that V NEW is changing
from
- R T is the sum of the R SET programming resistors
Component Selection For C SOFT Capacitor
Choosing the C SOFT capacitor to meet the requirements of a
particular soft-start delay t SS is calculated with Equation 20,
which is written as:
– t SS
(EQ. 20)
? V START-UP ?
? ?
Where:
-
- I SS is the soft-start current source at the 20μA limit
-
the state of the VID inputs at the time EN is asserted
- R T is the sum of the R SET programming resistors
Choosing the C SOFT capacitor to meet the requirements of a
particular voltage-step delay t VS is calculated with
t SS = – ( I SS ? C SOFT ) ? LN ( 1 – ------------------------------ )
I ? R
C SOFT = ------------------------------------------------------------------------------
? R T ? LN ( 1 – --------------------------------------- ) ?
V START-UP
SS T
13
(EQ. 18)
Equation 21, which is written as:
– t VS
? V NEW – V OLD ?
? ± I VS ? R T ?
(EQ. 21)
FN6707.0
August 14, 2008
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