参数资料
型号: ISL62881HRTZ
厂商: Intersil
文件页数: 19/35页
文件大小: 0K
描述: IC REG PWM SGL PHASE 28TQFN
标准包装: 75
应用: 控制器,Intel IMVP-6.5?
输入电压: 5 V ~ 25 V
输出数: 1
输出电压: 0.013 V ~ 1.5 V
工作温度: -10°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(4x4)
包装: 管件
ISL62881, ISL62881B
There are many sets of parameters that can properly
temperature-compensate the DCR change. Since the NTC
network and the R sum resistors form a voltage divider, V cn is
always a fraction of the inductor DCR voltage. It is recommended
to have a higher ratio of V cn to the inductor DCR voltage, so the
droop circuit has higher signal level to work with.
A typical set of parameters that provide good temperature
compensation are: R sum = 3.65k Ω , R p = 11k Ω , R ntcs = 2.61k Ω
and R ntc = 10k Ω (ERT-J1VR103J). The NTC network parameters
may need to be fine tuned on actual boards. One can apply full
load DC current and record the output voltage reading
immediately; then record the output voltage reading again when
the board has reached the thermal steady state. A good NTC
network can limit the output voltage drift to within 2mV. It is
recommended to follow the Intersil evaluation board layout and
current-sensing network parameters to minimize engineering
time.
For example, given R sum = 3.65k Ω , R p = 11k Ω , R ntcs = 2.61k Ω ,
R ntc = 10k Ω , DCR = 1.1m Ω and L = 0.45μH, Equation 12 gives
C n = 0.18μF.
Assuming the compensator design is correct, Figure 14 shows
the expected load transient response waveforms if C n is correctly
selected. When the load current I core has a square change, the
output voltage V core also has a square response.
If C n value is too large or too small, V Cn (s) will not accurately
represent real-time I o (s) and will worsen the transient response.
Figure 15 shows the load transient response when C n is too
small. V core will sag excessively upon load insertion and may
create a system failure. Figure 16 shows the transient response
when C n is too large. V core is sluggish in drooping to its final
value. There will be excessive overshoot if load insertion occurs
during this time, which may potentially hurt the CPU reliability.
L
C n = ------------------------------------------------------------
R ntcnet × R sum
V Cn (s) also needs to represent real-time I o (s) for the controller to
achieve good transient response. Transfer function A cs (s) has a
pole ω sns and a zero ω L . One needs to match ω L and ω sns so
A cs (s) is unity gain at all frequencies. By forcing ω L equal to ω sns
and solving for the solution, Equation 12 gives C n value.
(EQ. 12)
----------------------------------------- × DCR
R ntcnet + R sum
i O
RING
BACK
i L
V O
FIGURE 17. OUTPUT VOLTAGE RING BACK PROBLEM
i o
ISUM+
V o
FIGURE 14. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
Rntcs
Rntc
Rp
Cn.1
Rn
OPTIONAL
+
Cn.2 Vcn
-
ISUM-
Ri
i o
Rip
Cip
V o
FIGURE 15. LOAD TRANSIENT RESPONSE WHEN C n IS TOO SMALL
i o
V o
FIGURE 16. LOAD TRANSIENT RESPONSE WHEN C n IS TOO LARGE
19
OPTIONAL
FIGURE 18. OPTIONAL CIRCUITS FOR RING BACK REDUCTION
Figure 17 shows the output voltage ring back problem during
load transient response. The load current i o has a fast step
change, but the inductor current i L cannot accurately follow.
Instead, i L responds in first order system fashion due to the
nature of current loop. The ESR and ESL effect of the output
capacitors makes the output voltage V o dip quickly upon load
current change. However, the controller regulates V o according to
the droop current i droop , which is a real-time representation of i L ;
therefore it pulls V o back to the level dictated by i L , causing the
ring back problem. This phenomenon is not observed when the
output capacitors have very low ESR and ESL, such as all ceramic
capacitors.
FN6924.3
June 16, 2011
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