参数资料
型号: ISL6307ACRZ-T
厂商: Intersil
文件页数: 19/33页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 48-QFN
标准包装: 4,000
PWM 型: 电压模式
输出数: 6
频率 - 最大: 275kHz
占空比: 66.7%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 48-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL6307A
TABLE 1. VID CODE (Continued)
defined as
VID7
800mV
VID6 VID5
400mV 200mV
VID4
100mV
VID3
50mV
VID2
25mV
VID1 VID0 DAC
12.5mV 6.25mV VOLTAGE
V DROOP = I AVG R FB
(EQ. 8)
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0.63750
0.63125
0.62500
0.61875
The regulated output voltage is reduced by the droop voltage
V DROOP . The output voltage, as a function of load current, is
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed.
V OUT = V REF – V OFFSET – ? ------------- ------------------ R FB ?
? R ISEN ?
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0.61250
0.60625
0.60000
? I OUT R X ?
N
(EQ. 9)
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0.59375
0.58750
0.58125
0.57500
0.56875
0.56250
0.55625
V REF is the reference voltage and V OFS is the programmed
offset voltage. I OUT is the total output current of the
converter, R ISEN is the sense resistor in the ISEN line, N is
the number of active channels, and R FB is the feedback
resistor. R X has a value of DCR, resistor or R DS(ON) , or
R SENSE , depending on the sensing method.
Therefore, the equivalent load-line impedance, i.e. Droop
impedance, is equal to:
R LL = ------------ ------------------
R ISEN
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0.55000
0.54375
R FB R X
N
(EQ. 10)
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
1
0.53750
0.53125
0.52500
0.51875
0.51250
0.50625
0.50000
OFF
OFF
Output-Voltage Offset Programming
The ISL6307A allows the designer to accurately adjust the
offset voltage. When a resistor, R OFS , is connected between
OFS to VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I OFS ) to flow into OFS. If
R OFS is connected to ground, the voltage across it is
regulated to 0.4V, and I OFS flows out of OFS. A resistor
between DAC and REF, R REF , is selected so that the
product (I OFS x R OFS ) is equal to the desired offset voltage.
These functions are shown in Figure 9.
Once the desired output offset voltage has been determined,
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
use the following formulas to set R OFS :
For Positive Offset (connect R OFS to VCC):
1.6 × R REF
R OFS = ------------------------------
0.4 × R REF
R OFS = ------------------------------
Droop can help to reduce the output-voltage spike that
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 8, a current proportional to the average
current in all active channels, I AVG , flows from FB through a
load-line regulation resistor, R FB . The resulting voltage drop
across R FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
19
V OFFSET
For Negative Offset (connect R OFS to GND):
V OFFSET
(EQ. 11)
(EQ. 12)
FN9236.0
February 6, 2006
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