参数资料
型号: ISL6307ACRZ-T
厂商: Intersil
文件页数: 20/33页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 48-QFN
标准包装: 4,000
PWM 型: 电压模式
输出数: 6
频率 - 最大: 275kHz
占空比: 66.7%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 48-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL6307A
FB
of C REF is based on the time duration for 1 bit VID change
and the allowable delay time.
Assuming the microprocessor controls the VID change at 1
DYNAMIC
VID D/A
DAC
bit every T VID , the relationship between the time constant of
R REF and C REF network and T VID is given by Equation 13.
E/A
R REF
C REF R RE F = T VID
(EQ. 13)
REF
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
VCC
OR
GND
the controller begins soft-start. Once the output voltage is
within the proper window of operation, VR_RDY asserts a
logic 1.
+
OFS
VCC
-
1.6V R OFS
+
0.4V
-
ISL6307ACR
VCC GND
FIGURE 9. OUTPUT VOLTAGE OFFSET PROGRAMMING
WITH ISL6307A
Dynamic VID
Modern microprocessors need to make changes to their
core voltage as part of normal operation. They direct the
core-voltage regulator to do this by making changes to the
VID inputs during regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
manner. Supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core-voltage
regulator.
The ISL6307A checks the VID inputs six times every
ISL6307A INTERNAL CIRCUIT
POR ENABLE
CIRCUIT COMPARATOR
+
-
0.875V
+
-
0.875V
SOFT-START
AND
FAULT LOGIC
EXTERNAL CIRCUIT
+ 12 V
10k ?
EN_PWR
91 0?
EN_VTT
switching cycle. If the VID code is found to have been
changed, the controller waits half of a complete cycle before
executing a 12.5mV change. If during the half-cycle wait
period, the difference between DAC level and the new VID
code changes, no change is made. If the VID code is more
than 1 bit higher or lower than the DAC (not recommended),
the controller will execute 12.5mV changes six times per
cycle until VID and DAC are equal. It is for this reason that it
is important to carefully control the rate of VID stepping in 1-
bit increments.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network
composed of R REF and C REF is required for an ISL6307A
based voltage regulator (see Figure 8). The selection of
R REF is based on the desired offset as detailed above in
Output-Voltage Offset Programming section. The selection
20
FIGURE 10. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6307A
is released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6307A is guaranteed. Hysteresis between the
rising and falling thresholds assure that once enabled,
the ISL6307A will not inadvertently turn off unless the
bias voltage drops substantially (see Electrical
Specifications ).
2. The ISL6307A features an enable input (EN_PWR) for
power sequencing between the controller bias voltage
FN9236.0
February 6, 2006
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