参数资料
型号: ISL6307AIRZ
厂商: Intersil
文件页数: 27/33页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 48-QFN
标准包装: 43
PWM 型: 电压模式
输出数: 6
频率 - 最大: 275kHz
占空比: 66.7%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 48-VFQFN 裸露焊盘
包装: 管件
ISL6307A
board; whether through-hole components are permitted; and
the total board space available for power-supply circuitry.
Generally speaking, the most economical solutions are
those in which each phase handles between 20 and 30A. All
surface-mount designs will tend toward the lower end of this
current range. If through-hole MOSFETs and inductors can
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 26,
P UP , 1 ≈ V IN ? ------ + --------- ? ? ---- 1 ? f S
be used, higher per-phase currents are possible. In cases
where board space is the limiting constraint, current can be
pushed as high as 40A per phase, but these designs require
heat sinks and forced air to cool the MOSFETs, inductors
and heat-dissipating surfaces.
the required time for this commutation is t 1 and the
approximated associated power loss is P UP,1 .
I M I PP ? t ?
? N 2 ? ? 2 ?
(EQ. 26)
MOSFETS
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct; the switching
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t 2 . In Equation 27, the
approximate power loss is P UP,2 .
P UP , 2 ≈ V IN ? ------ – --------- ? ? ---- 2 ? f S
frequency; the capability of the MOSFETs to dissipate heat;
and the availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
? N 2 ? ? 2 ?
I M I PP ? t ?
(EQ. 27)
P UP , 3 ≈ V IN Q rr f S
The calculation for heat dissipated in the lower MOSFET is
simple, since virtually all of the heat loss in the lower
MOSFET is due to current conducted through the channel
resistance (R DS(ON) ). In Equation 24, I M is the maximum
continuous output current; I PP is the peak-to-peak inductor
current (see Equation 1); d is the duty cycle (V OUT /V IN ); and
L is the per-channel inductance.
A third component involves the lower MOSFET’s reverse-
recovery charge, Q rr . Since the inductor current has fully
commutated to the upper MOSFET before the lower-
MOSFET’s body diode can draw all of Q rr , it is conducted
through the upper MOSFET across VIN. The power
dissipation, P UP,3 , can be calculated from Equation 28.
(EQ. 28)
? I M ? 2 I L , PP ( 1 – d )
? ------ ? ( 1 – d ) + --------------------------------
P LOW , 1 = r DS ( ON )
? N ? 12
(EQ. 24)
approximately
Finally, the resistive part of the upper MOSFET’s is given in
An additional term can be added to the lower-MOSFET loss
Equation 29 as P UP,4 .
I PP2
? I M ?
P UP , 4 ≈ r DS ( ON ) ? ------ ? d + ---------- d
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
2
? N ? 12
(EQ. 29)
diode forward voltage at I M , V D(ON) ; the switching
frequency, f S ; and the length of dead times, t d1 and t d2 , at
the beginning and the end of the lower-MOSFET conduction
interval respectively.
The total power dissipated by the upper MOSFET, at full
load, can now be approximated as the summation of the
results from Equations 26, 27, 28 and 29. Since the power
equations depend on the MOSFET parameters, choosing
P LOW , 2 = V D ( ON ) f S ? ------ + I --------- ? t
I PP ?
? I
d1 + ? ------ – --------- ? t d2
I M PP
? N 2 ?
M
? N 2 ?
(EQ. 25)
the correct MOSFETs, can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Thus the total maximum power dissipated in each lower
MOSFET is approximated by the summation of P LOW,1 and
P LOW,2 .
UPPER MOSFET POWER CALCULATION
In addition to R DS(ON) losses, a large portion of the upper-
MOSFET losses are due to currents conducted across the
input voltage (V IN ) during switching. Since a substantially
higher portion of the upper-MOSFET losses are dependent
on switching frequency, the power calculation is more
complex. Upper MOSFET losses can be divided into
Current Sensing Resistor
The resistors connected between these ISEN+ pins and the
respective phase nodes (R DS(ON) Sensing) or the output
side of inductor (DCR sensing) determine the gains in the
load-line regulation loop and the channel-current balance
loop as well as setting the overcurrent trip point. Select
values for these resistors based on the room temperature
R DS(ON) of the lower MOSFETs, the DCR of inductor or
additional resistor; the full-load operating current, I FL ; and
the number of phases, N, using Equation 30.
R ISEN = -----------------------
I FL
separate components involving the upper-MOSFET
switching times; the lower-MOSFET body-diode reverse-
R X
50 × 10 – 6
--------
N
(EQ. 30)
recovery charge, Q rr ; and the upper MOSFET R DS(ON)
conduction loss.
27
FN9236.0
February 6, 2006
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