参数资料
型号: ISL6307AIRZ
厂商: Intersil
文件页数: 29/33页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 48-QFN
标准包装: 43
PWM 型: 电压模式
输出数: 6
频率 - 最大: 275kHz
占空比: 66.7%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 48-VFQFN 裸露焊盘
包装: 管件
ISL6307A
------------------- ≤ f 0 < ------------------------------
.
Case 2:
1 1
2 π LC 2 π C ( ESR )
type III controller, as shown in Figure 24, provides the
necessary compensation.
C 2
V PP ( 2 π ) 2 f 02 LC
R C = R FB --------------------------------------------
C C = -------------------------------------------------------------
PP R FB LC
( 2 π ) 2 f 2 V
0.75 V IN
0.75V IN
0
(EQ. 34)
R C
C C
COMP
FB
f 0 > ------------------------------
0.75 V IN ( ESR )
Case 3:
1
2 π C ( ESR )
2 π f 0 V pp L
R C = R FB ------------------------------------------
C 1
R 1
R FB
IDROOP
VDIFF
0.75V IN ( ESR ) C
2 π V PP R FB f 0 L
R 1 = R FB -----------------------------------------
C 1 = -----------------------------------------
0.75V IN
( 2 π ) 2 f 0 f HF LCR FB V PP
V PP ? 2 π ? f 0 f HF LCR FB
R C = ---------------------------------------------------------------------
? 2 π f
HF LC – 1 ?
?
?
0.75 V
C C = -------------------------------------------------
In Equation 34, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V PP is the peak-to-
peak sawtooth signal amplitude as described in Figure 7 and
Electrical Specifications .
The optional capacitor C 2 , is sometimes needed to bypass
noise away from the PWM comparator (see Figure 24). Keep
a position available for C 2 , and be prepared to install a high-
frequency capacitor of between 22pF and 150pF in case any
leading-edge jitter problem is noted.
Once selected, the compensation values in Equation 34
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R C . Slowly increase the
value of R C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C C will not need adjustment. Keep the value of C C from
Equation 34 unless some performance issue is noted.
COMPENSATION WITHOUT LOAD-LINE REGULATION
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
FIGURE 24. COMPENSATION CIRCUIT FOR ISL6307A BASED
CONVERTER WITHOUT LOAD-LINE
REGULATION
The first step is to choose the desired bandwidth, f 0 , of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, f HF . This pole can be used for
added noise rejection or to assure adequate attenuation at
the error-amplifier high-order pole and zero frequencies. A
good general rule is to choose f HF = 10f 0 , but it can be
higher if desired. Choosing f HF to be lower than 10f 0 can
cause problems with too much phase shift below the system
bandwidth.
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 35, R FB is selected arbitrarily. The remaining
compensation components are then selected according to
Equation 35.
C ( ESR )
LC – C ( ESR )
LC – C ( ESR )
R FB
C 2 = -------------------------------------------------------------------
2
? ?
IN
0.75V IN ? 2 π f
HF LC – 1 ?
C C = -------------------------------------------------------------------
?
?
( 2 π ) 2 f 0 f HF LCR FB V PP
(EQ. 35)
In Equation 35, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
29
FN9236.0
February 6, 2006
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