参数资料
| 型号： | ISL6307AIRZ |
| 厂商： | Intersil |
| 文件页数： | 28/33页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 48-QFN |
| 标准包装： | 43 |
| PWM 型： | 电压模式 |
| 输出数： | 6 |
| 频率 - 最大： | 275kHz |
| 占空比： | 66.7% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页当前第28页第29页第30页第31页第32页第33页
ISL6307A
R ISEN , 2 = R ISEN ---------- 2
In certain circumstances, it may be necessary to adjust the
value of one or more ISEN resistors. When the components
of one or more channels are inhibited from effectively
dissipating their heat so that the affected channels run hotter
than desired, choose new, smaller values of RISEN for the
affected phases (see the section entitled Channel-Current
Balance ). Choose R ISEN,2 in proportion to the desired
decrease in temperature rise in order to cause proportionally
less current to flow in the hotter phase.
? T
(EQ. 31)
? T 1
The final locations of these poles are determined by the
system function, the gain of the current signal, and the value
of the compensation components, R C and C C .
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal
In Equation 31, make sure that ? T 2 is the desired temperature
rise above the ambient temperature, and ? T 1 is the measured
temperature rise above the ambient temperature. While a
single adjustment according to Equation 31 is usually
transient performance.
C 2 (OPTIONAL)
sufficient, it may occasionally be necessary to adjust R ISEN
two or more times to achieve optimal thermal balance
R C
C C
COMP
between all channels.
Load-Line Regulation Resistor
FB
The load-line regulation resistor is labelled R FB in Figure 8.
Its value depends on the desired full-load droop voltage
(V DROOP in Figure 8). If Equation 30 is used to select each
ISEN resistor, the load-line regulation resistor is as shown in
R FB
+
V DROOP
-
IDROOP
VDIFF
Equation 32.
R FB = -------------------------
50 × 10
V DROOP
– 6
(EQ. 32)
FIGURE 23. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6307A CIRCUIT
If one or more of the ISEN resistors are adjusted for thermal
balance, as in Equation 31, the load-line regulation resistor
should be selected according to Equation 33 where I FL is the
full-load operating current and R ISEN(n) is the ISEN resistor
connected to the n th ISEN pin.
The feedback resistor, R FB , has already been chosen as
outlined in Load-Line Regulation Resistor . Select a target
bandwidth for the compensated system, f 0 . The target
bandwidth must be large enough to assure adequate
transient performance, but smaller than 1/3 of the per-
channel switching frequency. The values of the
R FB = --------------------------------
V DROOP
I FL r DS ( ON )
∑ R ISEN ( n )
n
(EQ. 33
compensation components depend on the relationships of f 0
to the L-C pole frequency and the ESR zero frequency. For
each of the three cases which follow, there are a separate
set of equations for the compensation components
------------------- > f 0
0.75V IN
C C = ------------------------------------
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
COMPENSATING LOAD-LINE REGULATED
CONVERTER
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
28
Case 1:
1
2 π LC
2 π f 0 V pp LC
R C = R FB ------------------------------------
0.75V IN
2 π V PP R FB f 0
FN9236.0
February 6, 2006
相关PDF资料 |
PDF描述 |
|---|---|
| ISL6307BIRZ | IC REG CTRLR BUCK PWM VM 48-QFN |
| ISL6307IRZ | IC REG CTRLR BUCK PWM VM 48-QFN |
| ISL6308AIRZ | IC CTRLR PWM BUCK 3PHASE 40-QFN |
| ISL6308IRZ | IC CTRLR PWM 3PHASE BUCK 40-QFN |
| ISL6310IRZ | IC CTRLR PWM 2PHASE BUCK 32-QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6307AIRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6307BCRZ | 功能描述:软开关 PWM 控制器 W/ANNEAL 6-PHS VR11 CNTRLR COM RoHS:否 制造商:Fairchild Semiconductor 输出端数量: 输出电流: 开关频率: 工作电源电压:30 V 电源电流: 最大工作温度:+ 105 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Reel |
| ISL6307BCRZ-T | 功能描述:软开关 PWM 控制器 W/ANNEAL 6-PHS VR11 CNTRLR COM TAPE AND RoHS:否 制造商:Fairchild Semiconductor 输出端数量: 输出电流: 开关频率: 工作电源电压:30 V 电源电流: 最大工作温度:+ 105 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Reel |
| ISL6307BIRZ | 功能描述:软开关 PWM 控制器 W/ANNEAL 6-PHS VR11 CNTRLR INDUSTRIAL RoHS:否 制造商:Fairchild Semiconductor 输出端数量: 输出电流: 开关频率: 工作电源电压:30 V 电源电流: 最大工作温度:+ 105 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Reel |
| ISL6307BIRZ-T | 功能描述:软开关 PWM 控制器 W/ANNEAL 6-PHS VR11 CNTRLR INDUSTRIAL RoHS:否 制造商:Fairchild Semiconductor 输出端数量: 输出电流: 开关频率: 工作电源电压:30 V 电源电流: 最大工作温度:+ 105 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。