参数资料
型号: ISL6307BCRZ-T
厂商: Intersil
文件页数: 10/33页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 48-QFN
标准包装: 4,000
PWM 型: 电压模式
输出数: 6
频率 - 最大: 275kHz
占空比: 66.7%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 48-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL6307B
Electrical Specifications
Operating Conditions: VCC = 5V or ICC < 25mA (Note 3). Unless Otherwise Specified (Continued)
PARAMETER
VR-RDY Reset Voltage
Overvoltage Protection Threshold
VDIFF Rising
Before valid VID
TEST CONDITIONS
MIN
58
1.250
TYP
60
1.275
MAX
62
1.300
UNITS
%VID
V
Overvoltage Reset Threshold
After valid VID, the voltage above VID
150
0.38
175
0.40
200
0.42
mV
V
OVP Output High Voltage
OVP Output Low Voltage
I OVP = 4mA
I OVP = 4mA
4.5
-
-
-
-
0.25
V
V
NOTES:
3. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.
4. Spec guaranteed by design.
5. During soft-start, VDAC rises from 0 to 1.1V first and then ramp to VID voltage after receiving valid VID input.
6. Soft-start ramp rate is determined by the adjustable soft-start oscillator frequency at the speed of 6.25mV per cycle.
Functional Pin Description
VCC - Supplies all the power necessary to operate the chip.
The controller starts to operate when the voltage on this pin
exceeds the rising POR threshold and shuts down when the
voltage on this pin drops below the falling POR threshold.
Connect this pin through a series 390 ? resistor to a +12V
supply and a 1μF capacitor from this pin to GND.
GND - Bias and reference ground for the IC. The bottom
metal base of ISL6307B is the GND.
EN_PWR - This pin is a threshold-sensitive enable input for
the controller. Connecting the 12V supply to EN_PWR
through an appropriate resistor divider provides a means to
synchronize power-up of the controller and the MOSFET
driver ICs. When EN_PWR is driven above 0.875V, the
ISL6307B is active depending on status of EN_VTT, the
internal POR, and pending fault states. Driving EN_PWR
below 0.745V will clear all fault states and prime the
ISL6307B to soft-start when re-enabled.
EN_VTT - This pin is another threshold-sensitive enable
input for the controller. It’s typically connected to VTT output
of VTT voltage regulator in the computer mother board.
When EN_VTT is driven above 0.875V, the ISL6307B is
active depending on status of ENLL, the internal POR, and
pending fault states. Driving EN_VTT below 0.745V will clear
all fault states and prime the ISL6307B to soft-start when re-
enabled.
FS - Use this pin to set up the desired switching frequency. A
resistor, placed from FS to ground will set the switching
frequency. The relationship between the value of the resistor
and the switching frequency will be described by an
approximate Equation 40.
SS - Use this pin to set up the desired start-up oscillator
frequency. A resistor, placed from SS to ground will set up
the soft-start ramp rate.The relationship between the value
of the resistor and the soft-start ramp up time will be
described by approximate equation.
10
VID7, VID6, VID5, VID4, VID3, VID2, VID1 and VID0 -
These are the inputs to the internal DAC that provides the
reference voltage for output regulation. Connect these pins
either to open-drain outputs with or without external pull-up
resistors or to active-pull-up outputs. VID7-VID0 have 40μA
internal pull-up current sources that diminish to zero as the
voltage rises above the logic-high level. These inputs can be
pulled up as high as VCC plus 0.3V.
When a VID code causes a shut-off, the controller needs to
be reset before it will start again.
VRSEL - VRSEL is the pin used to select Internal VID code.
when it is connected to GND, the extended VR10 code is
selected. When it’s floated or pulled to high, VR11 code is
selected. This input can be pulled up as high as VCC plus 0.3V.
VDIFF, VSEN, and RGND - VSEN and RGND form the
precision differential remote-sense amplifier. This amplifier
converts the differential voltage of the remote output to a
single-ended voltage referenced to local ground. VDIFF is
the amplifier ’s output and the input to the regulation and
protection circuitry. Connect VSEN and RGND to the sense
pins of the remote load.
FB and COMP - Inverting input and output of the error
amplifier respectively. FB is connected to VDIFF through a
resistor. A negative current, proportional to output current is
present on the FB pin. A properly sized resistor between
VDIFF and FB sets the load line (droop). The droop scale
factor is set by the ratio of the ISEN resistors and the lower
MOSFET R DS(ON) . COMP is tied back to FB through an
external R-C network to compensate the regulator.
DAC and REF - The DAC output pin is the output of the
precision internal DAC reference. The REF input pin is the
positive input of the Error Amp. In typical applications, a 1k ? ,
1% resistor is used between DAC and REF to generate a
precise offset voltage. This voltage is proportional to the
offset current determined by the offset resistor from OFS to
ground or VCC. A capacitor is used between REF and
ground to smooth the voltage transition during Dynamic
VID? operations.
FN9225.0
March 9, 2006
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