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参数资料
| 型号： | ISL6307BCRZ-T |
| 厂商： | Intersil |
| 文件页数： | 15/33页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 48-QFN |
| 标准包装： | 4,000 |
| PWM 型： | 电压模式 |
| 输出数： | 6 |
| 频率 - 最大： | 275kHz |
| 占空比： | 66.7% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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ISL6307B
the temperature effect on the sensed current signal, a
Positive Temperature Coefficient (PTC) resistor can be
voltage. The internal and external circuitry which control
voltage regulation is illustrated in Figure 8.
selected for the sense resistor R ISEN , or the integrated
temperature compensation function of ISL6307B should be
EXTERNAL CIRCUIT
ISL6307B INTERNAL CIRCUIT
utilized. The integrated temperature compensation function
is described in the Temperature Compensation section.
Channel-Current Balance
R C
C C
COMP
DAC
The sensed current I n from each active channel are summed
together and divided by the number of active channels. The
resulting average current I AVG provides a measure of the
total load current. Channel current balance is achieved by
R REF
C REF
REF
FB
+
-
V COMP
comparing the sampled current of each channel to the
average current to make an appropriate adjustment to the
PWM duty cycle of each channel. Intersil’s patented current-
R FB
+
V DROOP
-
IDROOP
VDIFF
I AVG
ERROR AMPLIFIER
balance method is illustrated in Figure 7. In the figure, the
average current combines with the channel 1 current I 1 to
create an error signal I ER . The filtered error signal modifies
the pulse width commanded by V COMP to correct any
unbalance and force I ER toward zero. The same method for
error signal correction is applied to each active channel.
V OUT +
V OUT -
VSEN
RGND
+
-
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
V COMP
+
-
+
-
PWM1
FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE
REGULATION WITH OFFSET ADJUSTMENT
The ISL6307B incorporates an internal differential remote-
FILTER
f(j ω )
I ER
+
I 1
-
SAWTOOTH SIGNAL
I AVG
÷ N Σ
I 6
I 5
I 4
I 3
I 2
sense amplifier in the feedback path. The amplifier removes
the voltage error encountered when measuring the output
voltage relative to the local controller ground reference point
resulting in a more accurate means of sensing output
voltage. Connect the microprocessor sense pins to the non-
inverting input, VSEN, and inverting input, RGND, of the
remote-sense amplifier. The remote-sense output, V DIFF , is
connected to the inverting input of the error amplifier through
FIGURE 7. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
Channel current balance is essential in achieving the
thermal advantage of multiphase operation. With good
current balance, the power loss is equally dissipated over
multiple devices and a greater area.
Voltage Regulation
The integrating compensation network shown in Figure 8
assures that the steady-state error in the output voltage is
limited only to the error in the reference voltage (output of
the DAC) and offset errors in the OFS current source,
remote-sense and error amplifiers. Intersil specifies the
guaranteed tolerance of the ISL6307B to include the
combined tolerances of each of these elements.
The output of the error amplifier, V COMP , is compared to the
sawtooth waveform to generate the PWM signals. The PWM
signals control the timing of the Intersil MOSFET drivers and
regulate the converter output to the specified reference
15
an external resistor.
A digital to analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID7
through VID0. The DAC decodes the 8-bit logic signal (VID)
into one of the discrete voltages shown in Table 1. Each VID
input offers a 45 μ A pull-up to an internal 2.5V source for use
with open-drain outputs. The pull-up current diminishes to
zero above the logic threshold to protect voltage-sensitive
output devices. External pull-up resistors can augment the
pull-up current sources if case leakage into the driving
device is greater than 45 μ A.
Load-Line Regulation
Some microprocessor manufacturers require a precisely-
controlled output resistance. This dependence of output
voltage on load current is often termed “droop” or “load line”
regulation. By adding a well controlled output impedance,
the output voltage can effectively be level shifted in a
direction which works to achieve the load-line regulation
required by these manufacturers.
FN9225.0
March 9, 2006
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6307BIRZ | 功能描述:软开关 PWM 控制器 W/ANNEAL 6-PHS VR11 CNTRLR INDUSTRIAL RoHS:否 制造商:Fairchild Semiconductor 输出端数量: 输出电流: 开关频率: 工作电源电压:30 V 电源电流: 最大工作温度:+ 105 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Reel |
| ISL6307BIRZ-T | 功能描述:软开关 PWM 控制器 W/ANNEAL 6-PHS VR11 CNTRLR INDUSTRIAL RoHS:否 制造商:Fairchild Semiconductor 输出端数量: 输出电流: 开关频率: 工作电源电压:30 V 电源电流: 最大工作温度:+ 105 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Reel |
| ISL6307CRZ | 功能描述:IC REG CTRLR BUCK PWM VM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6307CRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6307IRZ | 功能描述:IC REG CTRLR BUCK PWM VM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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