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| 型号： | ISL6307BCRZ-T |
| 厂商： | Intersil |
| 文件页数： | 21/33页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 48-QFN |
| 标准包装： | 4,000 |
| PWM 型： | 电压模式 |
| 输出数： | 6 |
| 频率 - 最大： | 275kHz |
| 占空比： | 66.7% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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ISL6307B
the controller will execute 12.5mV changes six times per
cycle until VID and DAC are equal. It is for this reason that it
is important to carefully control the rate of VID stepping in
1-bit increments.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network
composed of R REF and C REF is required for an ISL6307B
based voltage regulator. The selection of R REF is based on
the desired offset as detailed above in Output-Voltage Offset
Programming . The selection of C REF is based on the time
duration for 1-bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at
1-bit every T VID , the relationship between the time constant
of R REF and C REF network and T VID is given by
Equation 13.
following input conditions must be met before the ISL6307B
is released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6307B is guaranteed. Hysteresis between the
rising and falling thresholds assure that once enabled,
the ISL6307B will not inadvertently turn off unless the
bias voltage drops substantially (see Electrical
Specifications ).
2. The ISL6307B features an enable input (EN_PWR) for
power sequencing between the controller bias voltage
and another voltage rail. The enable comparator holds
the ISL6307B in shutdown until the voltage at EN_PWR
rises above 0.875V. The enable comparator has about
130mV of hysteresis to prevent bounce. It is important
that the driver ICs reach their POR level before the
C REF R REF = T VID
(EQ. 13)
ISL6307B becomes enabled. The schematic in Figure 10
demonstrates sequencing the ISL6307B with the
ISL66xx family of Intersil MOSFET drivers, which require
12V bias.
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, VR_RDY asserts a
logic 1.
3. The voltage on EN_VTT must be higher than 0.875V to
enable the controller. This pin is typically connected to the
output of VTT VR.
When all conditions above are satisfied, ISL6307B begins
the soft-start and ramps the output voltage to 1.1V first. After
remaining at 1.1V for some time, ISL6307B reads the VID
ISL6307B INTERNAL CIRCUIT
EXTERNAL CIRCUIT
code at VID input pins. If the VID code is valid, ISL6307B will
regulate the output to the final VID setting. If the VID code is
VCC
+ 12 V
OFF code, ISL6307B will shut down. Cycling Vcc, EN_PWR
or EN_VTT is needed to restart.
POR
CIRCUIT
ENABLE
COMPARATOR
+
-
0.875V
+
-
0.875V
10k ?
EN_PWR
91 0?
EN_VTT
Soft-start
ISL6307B based VR has 4 periods during soft-start, as
shown in Figure 11. After Vcc, EN_VTT and EN_PWR reach
their POR and enable thresholds, The controller will have
fixed delay period TD1. After this delay period, the VR will
begin first soft-start ramp until the output voltage reaches
1.1V, Vboot voltage. Then, the controller will regulate the VR
voltage at 1.1V for another fixed period, TD3. At the end of
TD3 period, ISL6307B will read the VID signals. If the VID
code is valid, ISL6307B will initiate the second soft-start
ramp until the voltage reaches the VID voltage minus offset
voltage.
The soft-start time is the sum of the 4 periods as shown in
SOFT-START
the following equation.
AND
FAULT LOGIC
T SS = TD1 + TD2 + TD3 + TD4
(EQ. 14)
FIGURE 10. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
21
TD1 is the fixed delay with typical value as 1.36ms. TD3 is
determined by the fixed 85μs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to valid the VID input is 500ns.
Therefore the minimum TD3 is about 86μs.
During TD2 and TD4, ISL6307B digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
FN9225.0
March 9, 2006
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6307BIRZ | 功能描述:软开关 PWM 控制器 W/ANNEAL 6-PHS VR11 CNTRLR INDUSTRIAL RoHS:否 制造商:Fairchild Semiconductor 输出端数量: 输出电流: 开关频率: 工作电源电压:30 V 电源电流: 最大工作温度:+ 105 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Reel |
| ISL6307BIRZ-T | 功能描述:软开关 PWM 控制器 W/ANNEAL 6-PHS VR11 CNTRLR INDUSTRIAL RoHS:否 制造商:Fairchild Semiconductor 输出端数量: 输出电流: 开关频率: 工作电源电压:30 V 电源电流: 最大工作温度:+ 105 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Reel |
| ISL6307CRZ | 功能描述:IC REG CTRLR BUCK PWM VM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6307CRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6307IRZ | 功能描述:IC REG CTRLR BUCK PWM VM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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