参数资料
| 型号： | ISL6310IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 13/27页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 2PHASE BUCK 32-QFN |
| 标准包装： | 6,000 |
| 应用： | 控制器，DDR |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 2.3 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
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ISL6310
If the R-C network components are selected such that the
R-C time constant matches the inductor L/DCR time
Once the desired output offset voltage has been determined,
use the following formulas to set R OFS :
R OFS = --------------------------
constant, then V DROOP is equal to the sum of the voltage
drops across the individual DCRs, multiplied by a gain. As
Equation 8 shows, V DROOP is therefore proportional to the
total output current, I OUT .
For Positive Offset (connect R OFS to GND):
0.5 ? R 1
V OFFSET
(EQ. 9)
V DROOP = --------------------- ? I OUT ? DCR
R OFS = --------------------------
R COMP
R S
L
V L (s)
DCR
(EQ. 8)
I OUT
For Negative Offset (connect R OFS to VCC):
1.5 ? R 1
V OFFSET
(EQ. 10)
PHASE1
INDUCTOR
V OUT
VDIFF
L 1
L 2
PHASE2
R S
R S
I
I
L
DCR
INDUCTOR
C OUT
+
V OFS
-
R 1
FB
I OFS
VREF
E/A
ISUM
ICOMP
C COMP
R COMP
-
-
1.5V
IREF
DROOP
V DROOP
+
ISL6310
C SUM
(OPTIONAL)
R OFS
OFS
GND
ISL6310
+
-
GND
0.5V
+
VCC
FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE
FIGURE 7. DCR SENSING CONFIGURATION
By simply adjusting the value of R S , the load line can be set
to any level, giving the converter the right amount of droop at
all load currents. It may also be necessary to compensate for
any changes in DCR due to temperature. These changes
-
VDIFF
PROGRAMMING
cause the load line to be skewed, and cause the R-C time
constant to not match the L/DCR time constant. If this
V OFS
+
R 1
VREF
E/A
becomes a problem a simple negative temperature
coefficient resistor network can be used in the place of
R COMP to compensate for the rise in DCR due to
temperature.
Output Voltage Offset Programming
The ISL6310 allows the designer to accurately adjust the offset
voltage by connecting a resistor, R OFS , from the OFS pin to
I OFS
VCC
FB
VCC or GND. When R OFS is connected between OFS and
VCC, the voltage across it is regulated to 1.5V. This causes a
proportional current (I OFS ) to flow into the OFS pin and out of
the FB pin. If R OFS is connected to ground, the voltage across
it is regulated to 0.5V, and I OFS flows into the FB pin and out of
R OFS
OFS
ISL6310
+
-
0.5V
-
+
1.5V
the OFS pin. The offset current flowing through the resistor
between VDIFF and FB will generate the desired offset voltage
which is equal to the product (I OFS x R 1 ). These functions are
shown in Figures 8 and 9.
GND
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
VCC
13
FN9209.4
August 7, 2008
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| ISL6312ACRZ-T | 功能描述:IC CTRLR PWM 4PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| ISL6312AIRZ | 功能描述:IC CTRLR PWM 4PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| ISL6312AIRZ-T | 功能描述:IC CTRLR PWM 4PHASE BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
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