参数资料
| 型号： | ISL6310IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 18/27页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 2PHASE BUCK 32-QFN |
| 标准包装： | 6,000 |
| 应用： | 控制器，DDR |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 2.3 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
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ISL6310
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 16,
the required time for this commutation is t 1 and the
approximated associated power loss is P UP,1 .
When designing the ISL6310 into an application, it is
recommended that the following calculation is used to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses,
P Qg_TOT , due to the gate charge of MOSFETs and the
integrated driver ’s internal circuitry and their corresponding
average driver current can be estimated with Equations 20
and 21, respectively.
I PP
I M
P UP , 1 ≈ V IN ? ? ------ + --------- ? ? ? ---- 1 ? ? F SW
P Qg_Q1 = --- ? Q G1 ? PVCC ? F SW ? N Q1 ? N PHASE
? N 2 ? ? 2 ?
? t ?
(EQ. 16)
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
3
2
(EQ. 20)
At turn on, the upper MOSFET begins to conduct and this
transition occurs over a time t 2 . In Equation 17, the
approximate power loss is P UP,2 .
P Qg_Q2 = Q G2 ? PVCC ? F SW ? N Q2 ? N PHASE
P UP , 2 ≈ V IN ? ? ------ – --------- ? ? ? ---- 2 ? ? F SW
I DR = ? --- ? Q G1 ? N
? I M I PP ? ? t ?
? N 2 ? ? 2 ?
(EQ. 17)
3
? 2
Q1
?
+ Q G2 ? N Q2 ? ? N PHASE ? F SW + I Q
(EQ. 21)
P UP , 3 = V IN ? Q rr ? F SW
A third component involves the lower MOSFET reverse
recovery charge, Q rr . Since the inductor current has fully
commutated to the upper MOSFET before the lower
MOSFET body diode can recover all of Q rr , it is conducted
through the upper MOSFET across VIN. The power
dissipated as a result is P UP,3 .
(EQ. 18)
Finally, the resistive part of the upper MOSFET is given in
Equation 19 as P UP,4 .
In Equations 20 and 21, P Qg_Q1 is the total upper gate drive
power loss and P Qg_Q2 is the total lower gate drive power
loss; the gate charge (Q G1 and Q G2 ) is defined at the
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I Q is the driver total
quiescent current with no load at both drive outputs; N Q1 and
N Q2 are the number of upper and lower MOSFETs per phase,
respectively; N PHASE is the number of active phases. The
I Q* VCC product is the quiescent power of the controller
without capacitive load and is typically 75mW at 300kHz.
The total gate drive power losses are dissipated among the
? I M ?
P UP , 4 ≈ r DS ( ON ) ? d ? ? ------ ?
I PP2
? N ?
2
+ ----------
12
(EQ. 19)
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
P BOOT = ---------------------
P DR_UP = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI1 + R EXT1 R LO1 + R EXT1 ?
P DR_LOW = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI2 + R EXT2 R LO2 + R EXT2 ?
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 16, 17, 18 and 19. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of two drivers
in the controller package, the total power dissipated by both
drivers must be less than the maximum allowable power
dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
path resistance, P DR_UP , the lower drive path resistance,
P DR_LOW , and in the boot strap diode, P BOOT . The rest of
the power will be dissipated by the external gate resistors
(R G1 and R G2 ) and the internal gate resistors (R GI1 and
R GI2 ) of the MOSFETs. Figures 15 and 16 show the typical
upper and lower gate drives turn-on transition path. The total
power dissipation in the controller itself, P DR , can be roughly
estimated as:
P DR = P DR_UP + P DR_LOW + P BOOT + ( I Q ? VCC )
(EQ. 22)
P Qg_Q1
3
? R HI1 R LO1 ? P Qg_Q1
3
? R HI2 R LO2 ? P Qg_Q2
2
R EXT1 = R G1 + -------------
R EXT2 = R G2 + -------------
temperature of +125°C. The maximum allowable IC power
dissipation for the 5x5 QFN package is approximately 4W at
paragraph for thermal transfer improvement suggestions.
18
R GI1
N Q1
R GI2
N Q2
FN9209.4
August 7, 2008
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