参数资料
| 型号： | ISL6310IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 21/27页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 2PHASE BUCK 32-QFN |
| 标准包装： | 6,000 |
| 应用： | 控制器，DDR |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 2.3 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 带卷 (TR) |
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ISL6310
per-channel switching frequency. The values of the
compensation components depend on the relationships of f 0
to the L-C pole frequency and the ESR zero frequency. For
each of the following three, there is a separate set of
equations for the compensation components.
Compensating the Converter operating without
Load-Line Regulation
The ISL6310 multi-phase converter operating without load
line regulation behaves in a similar manner to a voltage
mode controller. This section highlights the design
--------------------------- > F 0
R 2 = R 1 ? ------------------------------------------------------------
0.66 ? V
Case 1:
1
2 π ? L ? C
2 π ? F 0 ? V OSC ? L ? C
IN
consideration for a voltage-mode controller requiring external
compensation. To address a broad range of applications, a
type-3 feedback network is recommended (see Figure 21).
2 π ? V OSC ? R 1 ? f 0
--------------------------- ≤ F 0 < ---------------------------------
Case 2:
0.66 ? V IN
C 1 = -------------------------------------------------
1 1
2 π ? L ? C 2 π ? C ? ESR
C 3
R 2
C 2
C 1
COMP
FB
V OSC ? ( 2 π ) 2 ? F 0 ? L ? C
R 2 = R 1 ? ----------------------------------------------------------------
2
0.66 ? V IN
(EQ. 28)
R 3
R 1
VDIFF
ISL6310
C 1 = --------------------------------------------------------------------------------
( 2 π ) ? F 0 ? V OSC ? R 1 ? L ? C
2
0.66 ? V IN
FIGURE 21. COMPENSATION CONFIGURATION FOR
NON-LOAD-LINE REGULATED ISL6310 CIRCUIT
F 0 > ---------------------------------
Case 3:
1
2 π ? C ? ESR
Figure 22 highlights the voltage-mode control loop for a
R 2 = R 1 ? -----------------------------------------------
2 π ? V OSC ? R 1 ? F 0 ? L
(EQ. 29)
F LC = ---------------------------
F CE = ---------------------------------
2 π ? F 0 ? V OSC ? L
0.66 ? V IN ? ESR
0.66 ? V IN ? ESR ? C
C 2 = ---------------------------------------------------------------
In Equation 28, L is the per-channel filter inductance divided by
the number of active channels; C is the sum total of all output
capacitors; ESR is the equivalent series resistance of the bulk
output filter capacitance; and V OSC is the peak-to-peak
sawtooth signal amplitude as described in the “Electrical
Once selected, the compensation values in Equation 28
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R 2 . Slowly increase the
value of R 2 while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C 1 will not need adjustment. Keep the value of C 1 from
Equation 28 unless some performance issue is noted.
The optional capacitor C 2 , is sometimes needed to bypass
noise away from the PWM comparator (see Figure 20). Keep
a position available for C 2 , and be prepared to install a high
frequency capacitor of between 22pF and 150pF in case any
leading edge jitter problem is noted.
21
synchronous-rectified buck converter, applicable, with a
small number of adjustments, to the multi-phase ISL6310
circuit. The output voltage (V OUT ) is regulated to the
reference voltage, VREF, level. The error amplifier output
(COMP pin voltage) is compared with the oscillator (OSC)
modified saw-tooth wave to provide a pulse-width modulated
wave with an amplitude of V IN at the PHASE node. The
PWM wave is smoothed by the output filter (L and C). The
output filter capacitor bank’s equivalent series resistance is
represented by the series resistor ESR.
The modulator transfer function is the small-signal transfer
function of V OUT /V COMP . This function is dominated by a
DC gain, given by d MAX V IN /V OSC , and shaped by the
output filter, with a double pole break frequency at F LC and a
zero at F CE . For the purpose of this analysis, L and DCR
represent the individual channel inductance and its DCR
divided by 2 (equivalent parallel value of the two output
inductors), while C and ESR represents the total output
capacitance and its equivalent series resistance.
1 1
2 π ? L ? C 2 π ? C ? ESR
The compensation network consists of the error amplifier
(internal to the ISL6310) and the external R 1 to R 3 , C 1 to C 3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F 0 ; typically 0.1 to 0.3 of F SW ) and adequate
phase margin (better than 45°). Phase margin is the
difference between the closed loop phase at F 0dB and 180°.
The equations that follow relate the compensation network’s
poles, zeros and gain to the components (R 1 , R 2 , R 3 , C 1 , C 2 ,
FN9209.4
August 7, 2008
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