参数资料
型号: ISL6313CRZ-T
厂商: Intersil
文件页数: 18/33页
文件大小: 0K
描述: IC CTRLR PWM 2PHASE BUCK 36-QFN
产品培训模块: Solutions for Industrial Control Applications
标准包装: 4,000
应用: 控制器,Intel VR11,AMD CPU
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.5 V ~ 1.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 36-WFQFN 裸露焊盘
供应商设备封装: 36-TQFN 裸露焊盘(6x6)
包装: 带卷 (TR)
ISL6313
In other cases, the designer may determine that a more
For Negative Offset (connect R OFS to VCC):
R OFS = --------------------------
R OFS = --------------------------
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
1.6 ? R FB
V OFFSET
For Positive Offset (connect R OFS to GND):
0.3 ? R FB
V OFFSET
VSEN
(EQ. 12)
(EQ. 13)
crossing the upper specification limit.
As shown in Figure 7, a current proportional to the average
+
V OFS
-
R FB
VREF
E/A
current of all active channels, I AVG , flows from FB through a
load-line regulation resistor R FB . The resulting voltage drop
across R FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as Equation 9:
FB
I OFS
V DROOP = I AVG ? R FB
(EQ. 9)
V OUT = V REF – V OFS – ? ------------- ? ------------------ ? R FB ?
? ?
N
R ISEN
The regulated output voltage is reduced by the droop voltage
V DROOP . The output voltage as a function of load current is
derived by combining Equations 6, 8, and 9.
? I OUT DCR ?
(EQ. 10)
R OFS
OFS
GND
ISL6313
+
-
GND
0.3V
-
1.6V
+
VCC
In Equation 10, V REF is the reference voltage, V OFS is the
programmed offset voltage, I OUT is the total output current
of the converter, R ISEN is the internal sense resistor
connected to the ISEN+ pin, R FB is the feedback resistor, N
is the active channel number, and DCR is the Inductor DCR
value.
FIGURE 8. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
VSEN
-
R LL = ------------ ? ------------------
R ISEN
Therefore the equivalent loadline impedance, i.e. droop
impedance, is equal to:
R FB DCR
(EQ. 11)
N
V OFS
+
R FB
FB
I OFS
VREF
E/A
Output-Voltage Offset Programming
The ISL6313 allows the designer to accurately adjust the
offset voltage by connecting a resistor, R OFS , from the OFS
pin to VCC or GND. When R OFS is connected between OFS
VCC
and VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I OFS ) to flow into the OFS pin
and out of the FB pin, providing a negative offset. If R OFS is
connected to ground, the voltage across it is regulated to
R OFS
OFS
ISL6313
+
-
0.3V
-
+
1.6V
0.3V, and I OFS flows into the FB pin and out of the OFS pin,
providing a positive offset. The offset current flowing through
the resistor between VSEN and FB will generate the desired
offset voltage which is equal to the product (I OFS x R FB ).
These functions are shown in Figures 8 and 9.
Once the desired output offset voltage has been determined,
use Equations 12 and 13 to set R OFS :
GND
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
VCC
18
FN6448.2
September 2, 2008
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