参数资料
型号: ISL6314CRZ
厂商: Intersil
文件页数: 21/32页
文件大小: 0K
描述: IC CTRLR PWM 1PHASE BUCK 32-QFN
产品培训模块: Solutions for Industrial Control Applications
标准包装: 60
应用: 控制器,Intel VR11,AMD CPU
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.38 V ~ 1.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 管件
ISL6314
t d2 = 1.1 ? R SS ? 8 ? 10
– 3
( μ s )
(EQ. 16)
TABLE 5. ISL6314 SOFT_START TIMING SUMMARY
MODE TIME SLOT TIME
t d4 = V VID – 1.1 ? R SS ? 8 ? 10
– 3
( μ s )
(EQ. 17)
VR11
VR11
t d1
t d2
1.1ms
Equation 16
For example, when VID is set to 1.5V and the R SS is set at
100k Ω , the first soft-start ramp time t d2 will be 880μs and the
second soft-start ramp time t d4 will be 320μs.
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay t d5 . The typical value
for t d5 is 93μs.
AMD Soft-Start
VR11
VR11
VR11
AMD
AMD
Pre-Biased Soft-Start
t d3
t d4
t d5
t dA
t dB
93μs
Equation 17
93μs
1.1ms
Equation 18
OUTPUT PRECHARGED
ABOVE DAC LEVEL
V OUT , 500mV/DIV
OUTPUT PRECHARGED
BELOW DAC LEVEL
t dA
t dB
EN
PGOOD
GND>
GND>
V OUT (0.5V/DIV)
EN (5V/DIV)
500μs/DIV
T1 T2
T3
FIGURE 12. AMD SOFT-START WAVEFORMS
For the AMD 5-bit and 6-bit modes of operation, the
soft-start sequence is composed of two periods, as shown in
Figure 12. At the beginning of soft-start, the VID code is
immediately obtained from the VID pins, followed by a fixed
delay period t dA of typically 1.1ms. After this delay period the
ISL6314 will begin ramping the output voltage to the desired
DAC level at a fixed rate of 6.25mV per step. The time for
each step is determined by the frequency of the soft-start
oscillator which is defined by the resistor R SS on the SS pin.
The amount of time required to ramp the output voltage to
the final DAC voltage is referred to as t dB , and can be
calculated as shown in Equation 18.
FIGURE 13. SOFT-START WAVEFORMS FOR ISL6314-BASED
CONVERTER
The ISL6314 also has the ability to start up into a pre-charged
output, without causing any unnecessary disturbance. The FB
pin is monitored during soft-start, and should it be higher than
the equivalent internal ramping reference voltage, the output
drives hold both MOSFETs off. Once the internal ramping
reference exceeds the FB pin potential, the output drives are
enabled, allowing the output to ramp from the pre-charged
level to the final level dictated by the DAC setting. Should the
output be pre-charged to a level exceeding the DAC setting,
the output drives are enabled at the end of the soft-start
period, leading to an abrupt correction in the output voltage
down to the DAC-set level. See Figure 13.
t dB = V VID ? R
SS
? 8 ? 10
– 3
( μ s )
(EQ. 18)
Fault Monitoring and Protection
At the end of soft-start, PGOOD will immediately go high if
the VSEN voltage is within the undervoltage and overvoltage
limits.
Table 5 is a summary table of the typical soft-start timing for
both modes. The times listed are fixed delays; the variable
ones (defined by the equations) depend on the slope of the
ramp (1.25 mV/μs for a nominal 100k Ω R SS resistor), and
the amount of voltage excursion.
21
The ISL6314 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 14
outlines the interaction between the fault monitors and the
power-good signal.
FN6455.2
October 8, 2009
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