参数资料
型号: ISL6314CRZ
厂商: Intersil
文件页数: 26/32页
文件大小: 0K
描述: IC CTRLR PWM 1PHASE BUCK 32-QFN
产品培训模块: Solutions for Industrial Control Applications
标准包装: 60
应用: 控制器,Intel VR11,AMD CPU
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.38 V ~ 1.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 管件
ISL6314
(EQ. 30)
R COMP = ---------------------------------------
1. Choose an arbitrary value for C COMP . The recommended
value is 0.01μF.
2. Plug the inductor L and DCR component values, and the
values for C COMP chosen in Step 1, into Equation 30 to
calculate the value for R COMP .
L
DCR ? C COMP
Loadline Regulation Resistor
If loadline regulation is desired, the resistor on the FS pin,
R T , should be connected to Ground (the value of R T
separately selects the switching frequency, as per
Equation 42). The desired loadline, R LL , can be calculated
by Equation 33 where V DROOP is the desired droop voltage
at the full load current I FL .
I FL
3. Use the new value for R COMP obtained from
Equation 30, as well as the desired full load current, I FL ,
full load droop voltage, V DROOP , and inductor DCR in
Equation 31 to calculate the value for R S .
V DROOP
R LL = -------------------------
(EQ. 33)
R S = ------------------------- ? R COMP ? DCR
I FL
V DROOP
(EQ. 31)
Based on values for Equation 31, the desired loadline can
also be calculated from Equation 34.
R S
Due to errors in the inductance or DCR it may be necessary
to adjust the value of R 1 to match the time constants
correctly. The effects of time constant mismatch can be seen
R COMP ? DCR
R LL = ---------------------------------------
(EQ. 34)
R 1 , NEW = R 1 , OLD ? ----------
R APA = = = 5k Ω
V APA , TRIP 500mV
in the form of droop overshoot or undershoot during the
initial load transient spike, as shown in Figure 19. Follow the
steps outlined in the following to ensure the R-C and
inductor L/DCR time constants are matched accurately.
1. Capture a transient event with the oscilloscope set to
about L/DCR/2 (sec/div). For example, with L = 1μH and
DCR = 1m Ω , set the oscilloscope to 500μs/div.
2. Record Δ V1 and Δ V2 as shown in Figure 19.
3. Select new values, R 1,NEW , for the time constant resistor
based on the original value, R 1,OLD , using Equation 32.
Δ V 1 (EQ. 32)
Δ V 2
4. Replace R 1 with the new value and check to see that the
If no loadline regulation is required, the resistor on the FS
pin, R T , should be connected to the VCC pin (the value of
R T separately selects the switching frequency, as per
Equation 42).
APA Pin Component Selection
A 100μA current flows out of the APA pin and across R APA
to set the APA trip level. A 1000pF capacitor, C APA , should
also be placed across the R APA resistor to help with noise
immunity. An APA trip level of 500mV is recommended for
most applications. Use Equation 35 to set R APA to get the
desired APA trip level.
------------------------------- ----------------------------- (EQ. 35)
100 × 10 – 6 100 × 10 – 6
error is corrected. Repeat the procedure if necessary.
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
Δ V 2
Δ V 1
V OUT
I TRAN
Δ I
FIGURE 19. TIME CONSTANT MISMATCH BEHAVIOR
26
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
COMPENSATION WITH LOAD-LINE REGULATION
The load-line regulated converter behaves in a similar
manner to a peak current mode controller because the two
poles at the output filter L-C resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R C and C C , as shown in
Figure 20.
FN6455.2
October 8, 2009
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