参数资料
型号: ISL6314CRZ
厂商: Intersil
文件页数: 27/32页
文件大小: 0K
描述: IC CTRLR PWM 1PHASE BUCK 32-QFN
产品培训模块: Solutions for Industrial Control Applications
标准包装: 60
应用: 控制器,Intel VR11,AMD CPU
输入电压: 5 V ~ 12 V
输出数: 1
输出电压: 0.38 V ~ 1.6 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN 裸露焊盘(5x5)
包装: 管件
ISL6314
C 2 (OPTIONAL)
-------------------------------- > f 0
Case 1:
1
2 ? π ? L ? C
R C = R FB ? ----------------------------------------------------------
V
2 ? π ? V P-P ? R FB ? f 0
R C
C C
COMP
FB
ISL6314
2 ? π ? f 0 ? V P-P ? L ? C
IN
V IN
C C = ------------------------------------------------------
R FB
-------------------------------- ≤ f 0 < -------------------------------------
VDIFF
Case 2:
1 1
2 ? π ? L ? C 2 ? π ? C ? ESR
V P-P ? ( 2 ? π ) 2 ? f 02 ? L ? C
C C = ---------------------------------------------------------------------------------------
P-P ? R FB ?
( 2 ? π ) 2 ? f 2 ? V L ? C
FIGURE 20. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6314 CIRCUIT
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
V
R C = R FB ? ------------------------------------------------------------------
IN
V IN
0
(EQ. 36)
f 0 > -------------------------------------
R C = R FB ? ----------------------------------------------
V ? ESR
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator, by compensating the L-C
poles and the ESR zero of the voltage mode approximation,
yields a solution that is always stable with very close to ideal
Case 3:
1
2 ? π ? C ? ESR
2 ? π ? f 0 ? V P-P ? L
IN
2 ? π ? V P-P ? R FB ? f 0 ? L
transient performance.
Select a target bandwidth for the compensated system, f 0 .
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
switching frequency. The values of the compensation
components depend on the relationships of f 0 to the L-C
pole frequency and the ESR zero frequency. For each of the
following three, there is a separate set of equations for the
compensation components.
In Equation 36, L is the filter inductance; C is the sum total of
all output capacitors; ESR is the equivalent series resistance
of the bulk output filter capacitance; and V P-P is the
peak-to-peak sawtooth signal amplitude, as described in the
“Electrical Specifications” on page 6.
Once selected, the compensation values in Equation 36
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R C . Slowly increase the
value of R C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C C will not need adjustment. Keep the value of C C from
Equation 36 unless some performance issue is noted.
27
V IN ? ESR ? C
C C = ------------------------------------------------------------------
The optional capacitor C 2 , is sometimes needed to bypass
noise away from the PWM comparator (see Figure 20). Keep
a position available for C 2 , and be prepared to install a
high-frequency capacitor of between 22pF and 150pF in
case any leading edge jitter problem is noted. For the
solutions in Equation 36, R FB is selected arbitrarily, typically
in the 1k Ω to 5k Ω range.
COMPENSATION WITHOUT LOAD-LINE REGULATION
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A
type III controller, as shown in Figure 21, provides the
necessary compensation.
The first step is to choose the desired bandwidth, f 0 , of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, f HF . This pole can be used for
added noise rejection or to assure adequate attenuation at
the error-amplifier high-order pole and zero frequencies. A
good general rule is to choose f HF = 10f 0 , but it can be
higher if desired. Choosing f HF to be lower than 10f 0 can
cause problems with too much phase shift below the system
bandwidth.
FN6455.2
October 8, 2009
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