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| 型号： | ISL6322GCRZ |
| 厂商： | Intersil |
| 文件页数： | 23/39页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM BUCK 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，Intel VR10、VR11、AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.38 V ~ 1.99 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
| 产品目录页面： | 1248 (CN2011-ZH PDF) |
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ISL6322G
TD1 is a fixed delay with the typical value as 1.40ms. TD3 is
determined by the fixed 85μs plus the time to obtain valid
voltage to the final DAC voltage is referred to as TDB, and
can be calculated as shown in Equation 17.
TDB = -------------------------- ? ? --------------------- ?
3 ? 0.00625 ?
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore the minimum TD3 is about 86μs.
330 × 10
1 V VID
(EQ. 17)
During t D2 and t D4 , ISL6322G digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor R SS from SS pin to GND. The
second soft-start ramp time t D2 and t D4 can be calculated
based on Equations 15 and 16:
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay t DC . The typical value
for t DC can range between 1.5ms and 3.0ms.
OUTPUT PRECHARGED
ABOVE DAC LEVEL
1.1 ? R SS
6.25 ? 25
t D2 = ------------------------ ( μ s )
(EQ. 15)
OUTPUT PRECHARGED
BELOW DAC LEVEL
t D4 ( 2 ) = ---------------------------------------------------- ( μ s )
( V VID – 1.1 ) ? R SS
6.25 ? 25
(EQ. 16)
GND>
V OUT (0.5V/DIV)
For example, when VID is set to 1.5V and the R SS is set at
100k Ω , the first soft-start ramp time t D2 will be 704μs and the
second soft-start ramp time t D4 will be 256μs.
NOTE: If the SS pin is grounded, the soft-start ramp in t D2
and t D4 will be defaulted to a 6.25mV step frequency of
GND>
t1 t2
t3
EN (5V/DIV)
330kHz.
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay t D5 . The typical value
for t D5 is 440μs.
V OUT , 500mV/DIV
FIGURE 13. SOFT-START WAVEFORMS FOR
ISL6322G-BASED MULTIPHASE CONVERTER
Pre-Biased Soft-Start
The ISL6322G also has the ability to start up into a
pre-charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output
t DA
EN_VTT
t DB
t DC
to ramp from the pre-charged level to the final level dictated
by the DAC setting. Should the output be pre-charged to a
level exceeding the DAC setting, the output drives are
enabled at the end of the soft-start period, leading to an
abrupt correction in the output voltage down to the DAC-set
level.
PGOOD
500μs/DIV
FIGURE 12. AMD SOFT-START WAVEFORMS
AMD Soft-Start
For the AMD 5-bit and 6-bit modes of operation, the
soft-start sequence is composed of three periods, as shown
in Figure 12. At the beginning of soft-start, the VID code is
immediately obtained from the VID pins, followed by a fixed
delay period t DA . After this delay period the ISL6322G will
begin ramping the output voltage to the desired DAC level at
a fixed rate of 6.25mV per step, with a stepping frequency of
330kHz. The amount of time required to ramp the output
23
Fault Monitoring and Protection
The ISL6322G actively monitors output voltage and current
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 14
outlines the interaction between the fault monitors and the
power good signal.
Power Good Signal
The power good pin (PGOOD) is an open-drain logic output
that signals whether or not the ISL6322G is regulating the
output voltage within the proper levels, and whether any fault
FN6715.0
May 22, 2008
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