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| 型号： | ISL6322GCRZ |
| 厂商： | Intersil |
| 文件页数： | 32/39页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM BUCK 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，Intel VR10、VR11、AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.38 V ~ 1.99 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
| 产品目录页面： | 1248 (CN2011-ZH PDF) |
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ISL6322G
fully commutated to the upper MOSFET before the
lower-MOSFET body diode can recover all of Q rr , it is
conducted through the upper MOSFET across VIN. The
power dissipated as a result is P UP,3 .
In Equations 27 and 28, P Qg_Q1 is the total upper gate drive
power loss and P Qg_Q2 is the total lower gate drive power loss;
the gate charge (Q G1 and Q G2 ) is defined at the particular gate
to source drive voltage PVCC in the corresponding MOSFET
P UP , 3 = V IN ? Q rr ? f S
(EQ. 25)
data sheet; I Q is the driver total quiescent current with no load
at both drive outputs; N Q1 and N Q2 are the number of upper
I P-P2
? I M ?
P UP , 4 ≈ r DS ( ON ) ? d ? ? ------ ? + ----------
Finally, the resistive part of the upper MOSFET is given in
Equation 26 as P UP,4 .
2
(EQ. 26)
? N ? 12
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results from
and lower MOSFETs per phase, respectively; N PHASE is the
number of active phases. The I Q* VCC product is the quiescent
power of the controller without capacitive load and is typically
75mW at 300kHz.
PVCC BOOT
D
C GD
Equations 23, 24, 25 and 26. Since the power equations
depend on MOSFET parameters, choosing the correct
MOSFETs can be an iterative process involving repetitive
solutions to the loss equations for different MOSFETs and
R HI1
R LO1
UGATE
G
R G1
R GI1
C GS
C DS
Q1
different switching frequencies.
Package Power Dissipation
When choosing MOSFETs it is important to consider the
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three drivers
in the controller package, the total power dissipated by all three
drivers must be less than the maximum allowable power
dissipation for the QFN package.
S
PHASE
FIGURE 19. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
D
C GD
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
R HI2
R LO2
LGATE
G
R G2
R GI2
C GS
C DS
Q2
temperature of +125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W at
room temperature. See “Layout Considerations” on page 36 for
thermal transfer improvement suggestions.
When designing the ISL6322G into an application, it is
recommended that the following calculation is used to ensure
safe operation at the desired frequency for the selected
MOSFETs. The total gate drive power losses, P Qg_TOT , due to
the gate charge of MOSFETs and the integrated driver’s
internal circuitry and their corresponding average driver current
can be estimated with Equations 27 and 28, respectively.
S
FIGURE 20. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
the controller itself is the power dissipated in the upper drive
path resistance, P DR_UP , the lower drive path resistance,
P DR_UP , and in the boot strap diode, P BOOT .
P Qg_Q1 = --- ? Q G1 ? PVCC ? F SW ? N Q1 ? N PHASE
P BOOT = ---------------------
P DR_UP = ? ? ? ---------------------
? R HI1 + R EXT1 R LO1 + R EXT1 ?
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
3
2
P Qg_Q2 = Q G2 ? PVCC ? F SW ? N Q2 ? N PHASE
(EQ. 27)
P DR = P DR_UP + P DR_LOW + P BOOT + ( I Q ? VCC )
P Qg_Q1
3
? R HI1 R LO1 ? P Qg_Q1
-------------------------------------- + ----------------------------------------
3
(EQ. 29)
I DR = ? --- ? Q G1 ? N
P DR_LOW = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI2 + R EXT2 R LO2 + R EXT2 ?
R EXT1 = R G1 + ------------- R EXT2 = R G2 + -------------
N N
.
3
? 2
Q1
?
+ Q G2 ? N Q2 ? ? N PHASE ? F SW + I Q
(EQ. 28)
? R HI2 R LO2 ? P Qg_Q2
2
R GI1 R GI2
Q1 Q2
32
FN6715.0
May 22, 2008
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| ISL6322GCRZ-T | 功能描述:IC CTRLR PWM BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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| ISL6322GIRZ-T | 功能描述:IC CTRLR PWM BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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