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参数资料
| 型号： | ISL6322GCRZ |
| 厂商： | Intersil |
| 文件页数： | 24/39页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM BUCK 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，Intel VR10、VR11、AMD CPU |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.38 V ~ 1.99 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
| 产品目录页面： | 1248 (CN2011-ZH PDF) |
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ISL6322G
conditions exist. This pin should be tied to a +5V source
through a resistor.
During shutdown and soft-start PGOOD pulls low and
releases high after a successful soft-start and the output
voltage is operating between the undervoltage and
overvoltage limits. PGOOD transitions low when an
undervoltage, overvoltage, or overcurrent condition is
detected or when the controller is disabled by a reset from
EN, POR, or one of the no-CPU VID codes. In the event of
an overvoltage or overcurrent condition, the controller
latches off and PGOOD will not return high until after a
successful soft-start. In the case of an undervoltage event,
PGOOD will return high when the output voltage returns to
within the undervoltage.
changes depending on what mode of operation the controller
is in and what state the I 2 C registers and the VRSEL pin are
in. Tables 6 and 7 list what the OVP trip levels are under all
conditions (refer beginning on page 24 for details of
controlling OVP thresholds with I 2 C).
At the inception of an overvoltage event LGATE1 and
LGATE2 are commanded high and the PGOOD signal is
driven low. This turns on the all of the lower MOSFETs and
pulls the output voltage below a level that might cause
damage to the load. The LGATE outputs remain high and
until VDIFF falls 100mV below the OVP threshold that
tripped the overvoltage protection circuitry. The ISL6322G
will continue to protect the load in this fashion as long as the
overvoltage condition recurs.
Once an overvoltage condition ends, the ISL6322G latches
120μA OR
240μA
I SEN1 +I SEN2
-
OCP
+
-
OCL
+
170μA
I SEN1
off and must be reset by toggling EN, or through POR,
before a soft-start can be re-initiated.
TABLE 6. INTEL VR10 AND VR11 OVP THRESHOLDS
I 2 C OVP
VDAC
REPEAT FOR
EACH CHANNEL
MODE OF
OPERATION
DEFAULT
ALTERNATE
REGISTER
+175mV,
+250mV,
+350mV
+
OCP
-
IOUT
V OCP
Soft-Start
(t D1 and t D2 )
1.280V and
VDAC + 250mV
(higher of the two)
1.280V and
VDAC + 175mV
(higher of the two)
VRSEL
SOFT-START, FAULT
Soft-Start
(t D3 and t D4 )
VDAC + 250mV
VDAC + 175mV
AND CONTROL LOGIC
Normal Operation
VDAC + 250mV
VDAC + 175mV
V OVP
TABLE 7. AMD OVP THRESHOLDS
VSEN
RGND
+
-
x1
-
+
-
+
OV
UV
PGOOD
MODE OF
OPERATION
Soft-Start
Normal Operation
DEFAULT
2.200V and
VDAC + 250mV
(higher of the two)
VDAC + 250mV
ALTERNATE
2.200V and
VDAC + 175mV
(higher of the two)
VDAC + 175mV
VDIFF
One exception that overrides the overvoltage protection
0.60 x DAC
ISL6322G INTERNAL CIRCUITRY
circuitry is a dynamic VID transition in AMD modes of
operation. If a new VID code is detected during normal
FIGURE 14. POWER GOOD AND PROTECTION CIRCUITRY
Undervoltage Detection
The undervoltage threshold is set at 60% of the VID code.
When the output voltage (VSEN - RGND) is below the
undervoltage threshold, PGOOD gets pulled low. No other
action is taken by the controller. PGOOD will return high if
the output voltage rises above 70% of the VID code.
Overvoltage Protection
The ISL6322G constantly monitors the sensed output voltage
on the VDIFF pin to detect if an overvoltage event occurs.
When the output voltage rises above the OVP trip level
actions are taken by the ISL6322G to protect the
microprocessor load. The overvoltage protection trip level
24
operation, the OVP protection circuitry is disabled from the
beginning of the dynamic VID transition, until 50μs after the
internal DAC reaches the final VID setting. This is the only
time during operation of the ISL6322G that the OVP circuitry
is not active.
Pre-POR Overvoltage Protection
Prior to PVCC and VCC exceeding their POR levels, the
ISL6322G is designed to protect the load from any
overvoltage events that may occur. This is accomplished by
means of an internal 10k Ω resistor tied from PHASE to
LGATE, which turns on the lower MOSFET to control the
output voltage until the overvoltage event ceases or the input
power supply cuts off. For complete protection, the low side
FN6715.0
May 22, 2008
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| ISL6322GCRZ-T | 功能描述:IC CTRLR PWM BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6322GIRZ | 功能描述:IC CTRLR PWM BUCK 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:2,000 系列:- 应用:控制器，DSP 输入电压:4.5 V ~ 25 V 输出数:2 输出电压:最低可调至 1.2V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:30-TFSOP（0.173"，4.40mm 宽） 供应商设备封装:30-TSSOP 包装:带卷 (TR) |
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