参数资料
| 型号： | ISL6323IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 4/36页 |
| 文件大小： | 0K |
| 描述： | IC HYBRID CTRLR PWM MONO 48-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 带卷 (TR) |
第1页第2页第3页当前第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
ISL6323
Functional Pin Description (Continued)
PIN NUMBER
16
17, 18
19
20, 21, 22, 23,
43, 44, 45, 46
24
SYMBOL
RSET
FB, COMP
APA
ISEN1+, ISEN1-,
ISEN2+, ISEN2-,
ISEN3-, ISEN3+,
ISEN4-, ISEN4+
EN
DESCRIPTION
Connect this pin to the VCC pin through a resistor (RSET) to set the effective value of
the internal RISEN current sense resistors. The values of the RSET resistor should be no
less than 20k Ω and no more than 80k Ω . A 0.1μF capacitor should be placed in parallel to
the RSET resistor.
These pins are the internal error amplifier inverting input and output respectively of the
core VR controller. FB, VSEN and COMP are tied together through external R-C networks
to compensate the regulator.
Adaptive Phase Alignment (APA) pin for setting trip level and adjusting time constant. A
100μA current flows into the APA pin and by tying a resistor from this pin to COMP the
trip level for the Adaptive Phase Alignment circuitry can be set.
These pins are used for differentially sensing the corresponding channel output currents.
The sensed currents are used for channel balancing, protection, and core load line
regulation.
Connect ISEN1-, ISEN2-, ISEN3-, and ISEN4- to the node between the RC sense
elements surrounding the inductor of their respective channel. Tie the ISEN+ pins to the
VCORE side of their corresponding channel’s sense capacitor.
This pin is a threshold-sensitive (approximately 0.85V) system enable input for the
controller. Held low, this pin disables both CORE and NB controller operation. Pulled high,
the pin enables both controllers for operation.
When the EN pin is pulled high, the ISL6323 will be placed in either SVI or PVI mode.
The mode is determined by the latched value of VID1 on the rising edge of the EN signal.
A third function of this pin is to provide driver bias monitor for external drivers. A resistor
divider with the center tap connected to this pin from the drive bias supply prevents
enabling the controller before insufficient bias is provided to external driver. The resistors
should be selected such that when the POR-trip point of the external driver is reached,
the voltage at this pin meets the above mentioned threshold level.
25, 33
26, 32
PHASE2 and PHASE1 Connect these pins to the sources of the corresponding upper MOSFETs. These pins are
the return path for the upper MOSFET drives.
UGATE2 and UGATE1 Connect these pins to the corresponding upper MOSFET gates. These pins are used to
control the upper MOSFETs and are monitored for shoot-through prevention purposes.
Maximum individual channel duty cycle is limited to 93.3%.
27, 31
BOOT2 and BOOT1
These pins provide the bias voltage for the corresponding upper MOSFET drives. Connect
these pins to appropriately chosen external bootstrap capacitors. Internal bootstrap
diodes connected to the PVCC1_2 pin provide the necessary bootstrap charge.
28, 30
LGATE2 and LGATE1 These pins are used to control the lower MOSFETs. Connect these pins to the
corresponding lower MOSFETs’ gates.
29
34
35, 36
37
38
PVCC1_2
PWROK
PWM3 and PWM4
VDDPWRGD
PHASE_NB
4
The power supply pin for the multi-phase internal MOSFET drivers. Connect this pin to
any voltage from +5V to +12V depending on the desired MOSFET gate-drive level.
Decouple this pin with a quality 1.0μF ceramic capacitor.
System wide Power-Good signal. If this pin is low, the two SVI bits are decoded to
determine the “metal VID”. When the pin is high, the SVI is actively running its protocol.
Pulse-width modulation outputs. Connect these pins to the PWM input pins of an Intersil
driver IC if 3- or 4-phase operation is desired. Connect the ISEN- pins of the channels
not desired to +5V to disable them and configure the core VR controller for 2-phase or
3-phase operation.
During normal operation this pin indicates whether both output voltages are within
specified overvoltage and undervoltage limits. If either output voltage exceeds these
limits or a reset event occurs (such as an overcurrent event), the pin is pulled low. This
pin is always low prior to the end of soft-start.
Connect this pin to the source of the corresponding upper MOSFET. This pin is the return
path for the upper MOSFET drive. This pin is used to monitor the voltage drop across the
upper MOSFET for overcurrent protection.
FN9278.5
May 17, 2011
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6324ACRZ | 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324ACRZR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONTROLLER, CORE+NORTHBRIDGE, PROG PSI, 3.4MHZ SVI - Rail/Tube 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
| ISL6324ACRZ-T | 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324ACRZ-TR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONT., CORE + NORTHBRIDGE, PROG PSI, 3.4MHZ SVI, 5 - Tape and Reel 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
| ISL6324AIRZ | 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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