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参数资料
| 型号： | ISL6326BCRZ-T |
| 厂商： | Intersil |
| 文件页数： | 20/30页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 40-QFN |
| 标准包装： | 4,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 275kHz |
| 占空比： | 25% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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ISL6326B
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore the minimum TD3 is about 86μs.
During TD2 and TD4, ISL6326B digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor R SS from SS pin to GND. The
second soft-start ramp time TD2 and TD4 can be calculated
based on the following equations:
either the DCR of the inductor or R SENSE depending on the
sensing method.
The resistor from the IOUT pin to GND should be chosen to
ensure that the voltage at the IOUT pin is less than 2V under
the maximum load current. If the IOUT pin voltage is higher
than 2V, overcurrent shutdown will be triggered, as
described in the Overcurrent Protection section.
A small capacitor can be placed between the IOUT pin and
GND to reduce the noise impact. If this pin is not used, tie it
1.1xR SS
( V VID – 1.1 ) xR SS
TD2 = ------------------------ ( μ s )
6.25x25
TD4 = ------------------------------------------------ ( μ s )
6.25x25
(EQ. 15)
(EQ. 16)
to GND.
Fault Monitoring and Protection
The ISL6326B actively monitors output voltage and current
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
For example, when VID is set to 1.5V and the R SS is set at
100k Ω , the first soft-start ramp time TD2 will be 704μs and
the second soft-start ramp time TD4 will be 256μs.
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay TD5. The
typical value for TD5 is 85μs.
VOUT, 500mV/DIV
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 9 outlines
the interaction between the fault monitors and the VR_RDY
signal.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output to indicate
that the soft-start period has completed and the output
voltage is within the regulated range. VR_RDY is pulled low
during shutdown and releases high after a successful soft-
start and a fixed delay TD5. VR_RDY will be pulled low when
an undervoltage or overvoltage condition is detected, or the
controller is disabled by a reset from EN_PWR, EN_VTT,
POR, or VID OFF-code.
TD1
TD2
TD3 TD4
TD5
Undervoltage Detection
The undervoltage threshold is set at 50% of the VID code.
EN_VTT
VR_RDY
500μs/DIV
FIGURE 8. SOFT-START WAVEFORMS
Current Sense Output
The current flowing out of the IOUT pin is equal to the
sensed average current inside ISL6326B. In typical
application, a resistor is placed from the IOUT pin to GND to
generate a voltage, which is proportional to the load current
and the resistor value:
When the output voltage at VSEN is below the undervoltage
threshold, VR_RDY is pulled low.
Overvoltage Protection
Regardless of the VR being enabled or not, the ISL6326B
overvoltage protection (OVP) circuit will be active after its
POR. The OVP thresholds are different under different
operation conditions. When VR is not enabled and during
the soft-start intervals TD1, TD2 and TD3, the OVP
threshold is 1.275V. Once the controller detects valid VID
input, the OVP trip point will be changed to DAC plus
175mV.
Two actions are taken by the ISL6326B to protect the
microprocessor load when an overvoltage condition occurs.
V IOUT = ------------------- ------------------ I LOAD
R ISEN
R IOUT R X
N
(EQ. 17)
At the inception of an overvoltage event, all PWM outputs
are commanded low instantly (less than 20ns). This causes
the Intersil drivers to turn on the lower MOSFETs and pull
where V IOUT is the voltage at the IOUT pin, R IOUT is the
resistor between the IOUT pin and GND, I LOAD is the total
output current of the converter, R ISEN is the sense resistor
connected to the ISEN+ pin, N is the active channel number,
and R X is the DC resistance of the current sense element,
20
the output voltage below a level to avoid damaging the load.
When the VDIFF voltage falls below the DAC plus 75mV,
PWM signals enter a high-impedance state. The Intersil
drivers respond to the high-impedance input by turning off
both upper and lower MOSFETs. If the overvoltage condition
reoccurs, the ISL6326B will again command the lower
FN9286.0
April 21, 2006
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6326BIRZ | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR IND RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326BIRZ-T | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR IND RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326CRZ | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR COM RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326CRZ-T | 功能描述:电流型 PWM 控制器 W/ANNEAL 4-PHS VR11 CNTRLR COM RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6326CRZ-TR5453 | 制造商:Intersil Corporation 功能描述:STD. ISL6326CRZ-T W/GOLD BOND WIRE ONLY - Tape and Reel |
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