参数资料
型号: ISL6326BCRZ-T
厂商: Intersil
文件页数: 26/30页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 40-QFN
标准包装: 4,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 275kHz
占空比: 25%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 40-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL6326B
Based on the desired loadline R LL , the loadline regulation
resistor can be calculated by the following equation:
C 2 (OPTIONAL)
NR R
R FB = ----------------------------------
ISEN LL
R X
(EQ. 33)
R C
C C
COMP
where N is the active channel number, R ISEN is the sense
resistor connected to the ISEN+ pin, and R X is the
resistance of the current sense element, either the DCR of
+
FB
the inductor or R SENSE depending on the sensing method.
R FB
V DROOP
If one or more of the current sense resistors are adjusted for
thermal balance, as in Equation 31, the load-line regulation
resistor should be selected based on the average value of
the current sensing resistors, as given in the following
-
VDIFF
equation:
FIGURE 16. COMPENSATION CONFIGURATION FOR
R X
R LL
R FB = ----------
∑ R ISEN ( n )
n
(EQ. 34)
LOAD-LINE REGULATED ISL6326B CIRCUIT
The feedback resistor, R FB , has already been chosen as
outlined in Load-Line Regulation Resistor . Select a target
where R ISEN(n) is the current sensing resistor connected to
the n th ISEN+ pin.
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in Load-Line Regulation, there are two distinct
methods for achieving these goals.
bandwidth for the compensated system, f 0 . The target
bandwidth must be large enough to assure adequate
transient performance, but smaller than 1/3 of the
per-channel switching frequency. The values of the
compensation components depend on the relationships of f 0
to the L-C pole frequency and the ESR zero frequency. For
each of the three cases which follow, there is a separate set
of equations for the compensation components.
------------------- > f 0
R C = R FB ------------------------------------
0.75V
2 π V PP R FB f 0
------------------- ≤ f 0 < ------------------------------
COMPENSATING LOAD-LINE REGULATED
CONVERTER
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R C and C C .
Case 1:
Case 2:
1
2 π LC
2 π f 0 V pp LC
IN
0.75V IN
C C = ------------------------------------
1 1
2 π LC 2 π C ( ESR )
R C = R FB --------------------------------------------
0.75 V
C C = -------------------------------------------------------------
PP R FB LC
( 2 π ) 2 f 2 V
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
V PP ( 2 π ) 2 f 02 LC
IN
0.75V IN
0
(EQ. 35)
f 0 > ------------------------------
0.75 V IN ( ESR )
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal
transient performance.
Case 3:
1
2 π C ( ESR )
2 π f 0 V pp L
R C = R FB ------------------------------------------
2 π V PP R FB f 0 L
0.75V IN ( ESR ) C
C C = -------------------------------------------------
In Equation 35, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
26
FN9286.0
April 21, 2006
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