参数资料
| 型号： | ISL6334BIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 19/30页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM SYNC BUCK 40-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，Intel VR11.1 |
| 输入电压： | 3 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 带卷 (TR) |
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ISL6334B, ISL6334C
direction, which works to achieve the load-line regulation
For Positive Offset (connect R OFS to VCC):
R OFS = ----------------------------
R OFS = ----------------------------
required by these manufacturers.
In other cases, the designer may determine that a more
cost-effective solution can be achieved by adding droop.
Droop can help to reduce the output-voltage spike that
results from fast load-current demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
1.6 ? R REF
V OFFSET
For Negative Offset (connect R OFS to GND):
0.4 ? R REF
V OFFSET
FB
DYNAMIC
(EQ. 11)
(EQ. 12)
DAC
crossing the upper specification limit.
As shown in Figure 6, a current proportional to the average
VID D/A
R REF
current of all active channels, I AVG , flows from FB through a
load-line regulation resistor R FB . The resulting voltage drop
across R FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as shown in Equation 8:
E/A
REF
C REF
V DROOP = I AVG ? R
FB
(EQ. 8)
VCC
The regulated output voltage is reduced by the droop voltage
V DROOP . The output voltage as a function of load current is
OR
GND
V OUT = V REF – V OFS – ? ----------------- ------------------ R FB ?
? ?
N
R ISEN
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed, as shown in Equation 9:
? I LOAD R X ?
(EQ. 9)
1.6V
-
+
VCC
0.4V
+
-
GND
ISL6334B, ISL6334C
OFS
R OFS
where V REF is the reference voltage, V OFS is the
programmed offset voltage, I LOAD is the total output current
of the converter, R ISEN is the sense resistor connected to
the ISEN+ pin, and R FB is the feedback resistor, N is the
active channel number, and R X is the DCR, or R SENSE
depending on the sensing method.
Therefore, the equivalent loadline impedance, i.e. Droop
impedance, is equal to Equation 10:
FIGURE 7. OUTPUT VOLTAGE OFFSET PROGRAMMING
Dynamic VID
Modern microprocessors need to make changes to their
core voltage as part of normal operation. They direct the
core-voltage regulator to do this by making changes to the
VID inputs during regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
R LL = ------------ ------------------
R ISEN
R FB R X
N
(EQ. 10)
manner. Supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core-voltage
Output-Voltage Offset Programming
The ISL6334B, ISL6334C allows the designer to accurately
adjust the offset voltage. When a resistor, R OFS , is
connected between OFS to VCC, the voltage across it is
regulated to 1.6V. This causes a proportional current (I OFS )
to flow into OFS. If R OFS is connected to ground, the voltage
across it is regulated to 0.4V, and I OFS flows out of OFS. A
resistor between DAC and REF, R REF , is selected so that
the product (I OFS x R OFS ) is equal to the desired offset
voltage. These functions are shown in Figure 7.
Once the desired output offset voltage has been determined,
use Equations 11 and 12 to calculate R OFS :
19
regulator.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network,
composed of R REF and C REF , as shown in Figure 7, can be
used. The selection of R REF is based on the desired offset
duration for 1-bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at
1-bit every t VID , the relationship between the time constant
of R REF and C REF network and t VID is given by Equation 13.
FN6689.2
August 31, 2010
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| ISL6334CCRZ | 功能描述:IC CTRLR PWM SYNC BUCK 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6334CCRZ-T | 功能描述:IC CTRLR PWM SYNC BUCK 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6334CIRZ | 功能描述:IC CTRLR PWM SYNC BUCK 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:2,000 系列:- 应用:控制器，DSP 输入电压:4.5 V ~ 25 V 输出数:2 输出电压:最低可调至 1.2V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:30-TFSOP（0.173"，4.40mm 宽） 供应商设备封装:30-TSSOP 包装:带卷 (TR) |
| ISL6334CIRZ-T | 功能描述:IC CTRLR PWM SYNC BUCK 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6334CRZ | 功能描述:IC CTRLR PWM 4PHASE BUCK 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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