参数资料
| 型号： | ISL6334BIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 20/30页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM SYNC BUCK 40-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，Intel VR11.1 |
| 输入电压： | 3 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 带卷 (TR) |
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ISL6334B, ISL6334C
2. The ISL6334B, ISL6334C features an enable input
C REF ? R
= t VID
(EQ. 13)
REF
During dynamic VID transition and VID steps up, the
overcurrent trip point increases by 140% to avoid falsely
triggering OCP circuits, while the overvoltage trip point is set
to its maximum VID OVP trip level. If the dynamic VID occurs
at PSI# asserted, the system should exit PSI# and complete
the transition, and then resume PSI# operation 50μs after
the transition.
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, VR_RDY asserts
logic high.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6334B,
ISL6334C is released from shutdown mode.
(EN_PWR) for power sequencing between the controller
bias voltage and another voltage rail. The enable
comparator holds the ISL6334B, ISL6334C in shutdown
until the voltage at EN_PWR rises above 0.875V. The
enable comparator has about 130mV of hysteresis to
prevent bounce. It is important that the driver reach their
POR level before the ISL6334B, ISL6334C becomes
enabled. The schematic in Figure 8 demonstrates
sequencing the ISL6334B, ISL6334C with the ISL66xx
family of Intersil MOSFET drivers, which require 12V
bias.
3. The voltage on EN_VTT must be higher than 0.875V to
enable the controller. This pin is typically connected to the
output of VTT VR.
When all conditions previously mentioned are satisfied,
ISL6334B, ISL6334C begins the soft-start and ramps the
output voltage to 1.1V first. After remaining at 1.1V for some
time, ISL6334B, ISL6334C reads the VID code at VID input
pins. If the VID code is valid, ISL6334B, ISL6334C will
regulate the output to the final VID setting. If the VID code is
OFF code, ISL6334B, ISL6334C will shut down, and cycling
VCC, EN_PWR or EN_VTT is needed to restart.
ISL6334B, ISL6334C
EXTERNAL CIRCUIT
Soft-Start
ISL6334B, ISL6334C based VR has 4 periods during soft-start,
VCC
+ 12 V
as shown in Figure 9. After VCC, EN_VTT and EN_PWR reach
their POR/enable thresholds, the controller will have a fixed
POR
CIRCUIT
ENABLE
COMPARATOR
+
-
100k Ω
EN_PWR
9.1k Ω
delay period t D1 . After this delay period, the VR will begin first
soft-start ramp until the output voltage reaches 1.1V V BOOT
voltage. Then, the controller will regulate the VR voltage at 1.1V
for another fixed period t D3 . At the end of t D3 period, ISL6334B,
ISL6334C reads the VID signals. If the VID code is valid,
ISL6334B, ISL6334C will initiate the second soft-start ramp until
0.875V
+
-
0.875V
EN_VTT
the voltage reaches the VID voltage minus offset voltage.
VOUT, 500mV/DIV
SOFT-START
t D1
t D2
t D3 t D4
t D5
AND
FAULT LOGIC
FIGURE 8. POWER SEQUENCING USING THRESHOLD-
EN_VTT
VR_RDY
SENSITIVE ENABLE (EN) FUNCTION
500μs/DIV
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6334B, ISL6334C are guaranteed. Hysteresis
FIGURE 9. SOFT-START WAVEFORMS
The soft-start time is the sum of the 4 periods, as shown in
Equation 14.
between the rising and falling thresholds assure that once
enabled, ISL6334B, ISL6334C will not inadvertently turn
t SS = t D1 + t D2 + t D3 + t D4
(EQ. 14)
off unless the bias voltage drops substantially (see
“Electrical Specifications” table beginning on page 8).
20
t D1 is a fixed delay with the typical value as 1.36ms. t D3 is
determined by the fixed 85μs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
FN6689.2
August 31, 2010
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相关代理商/技术参数 |
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| ISL6334CCRZ | 功能描述:IC CTRLR PWM SYNC BUCK 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6334CCRZ-T | 功能描述:IC CTRLR PWM SYNC BUCK 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6334CIRZ | 功能描述:IC CTRLR PWM SYNC BUCK 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:2,000 系列:- 应用:控制器，DSP 输入电压:4.5 V ~ 25 V 输出数:2 输出电压:最低可调至 1.2V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:30-TFSOP（0.173"，4.40mm 宽） 供应商设备封装:30-TSSOP 包装:带卷 (TR) |
| ISL6334CIRZ-T | 功能描述:IC CTRLR PWM SYNC BUCK 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6334CRZ | 功能描述:IC CTRLR PWM 4PHASE BUCK 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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