参数资料
| 型号： | ISL6334BIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 21/30页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM SYNC BUCK 40-QFN |
| 标准包装： | 4,000 |
| 应用： | 控制器，Intel VR11.1 |
| 输入电压： | 3 V ~ 12 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 1.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 供应商设备封装： | 40-QFN（6x6） |
| 包装： | 带卷 (TR) |
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ISL6334B, ISL6334C
1.1V, the minimum time to validate the VID input is 500ns.
Therefore, the minimum t D3 is about 86μs.
During t D2 and t D4 , ISL6334B, ISL6334C digitally controls
the DAC voltage change at 6.25mV per step. The time for
each step is determined by the frequency of the soft-start
oscillator, which is defined by the resistor R SS from SS pin to
outlines the interaction between the fault monitors and the
VR_RDY signal.
UV
( V VID – 1.1 ) ? R SS
t D4 = ------------------------------------------------- ( μ s )
GND. The second soft-start ramp time t D2 and t D4 can be
calculated based on Equations 15 and 16:
(EQ. 16)
6.25 ? 25
50%
DAC
+
OC
-
105μA
I AVG
1.1 ? R SS
6.25 ? 25
t D2 = ------------------------ ( μ s )
(EQ. 15)
SOFT-START, FAULT
AND CONTROL LOGIC
For example, when VID is set to 1.5V and the R SS is set at
100k Ω , the first soft-start ramp time t D2 will be 704μs and the
second soft-start ramp time t D4 will be 256μs.
After the DAC voltage reaches the final VID setting,
VDIFF
+
-
OV
+
OC
-
1.11V
IMON
VR_RDY will be set to high with the fixed delay t D5 . The
V IOUT = ------------------- ------------------ I LOAD
R ISEN
typical value for t D5 is 85μs. Before the VR_RDY is
released, the controller disregards the PSI# input and
always operates in normal CCM PWM mode.
Current Sense Output
The current flowing out of the IMON pin is equal to the
sensed average current inside ISL6334B, ISL6334C. In
typical applications, a resistor is placed from the IMON pin to
GND to generate a voltage, which is proportional to the load
current and the resistor value, as shown in Equation 17:
R IOUT R X (EQ. 17)
N
where V IMON is the voltage at the IMON pin, R IMON is the
resistor between the IMON pin and GND, I LOAD is the total
output current of the converter, R ISEN is the sense resistor
connected to the ISEN+ pin, N is the active channel number,
and R X is the DC resistance of the current sense element,
either the DCR of the inductor or R SENSE depending on the
sensing method.
The resistor from the IMON pin to GND should be chosen to
ensure that the voltage at the IMON pin is less than 1.11V
under the maximum load current. If the IMON pin voltage is
higher than 1.11V, overcurrent shutdown will be triggered, as
A small capacitor can be placed between the IMON pin and
GND to reduce the noise impact. If this pin is not used, tie it
to GND.
Fault Monitoring and Protection
The ISL6334B, ISL6334C actively monitors output voltage and
current to detect fault conditions. Fault monitors trigger
protective measures to prevent damage to a microprocessor
load. One common power-good indicator is provided for linking
to external system monitors. The schematic in Figure 10
21
VID + 0.175V
FIGURE 10. VR_RDY AND PROTECTION CIRCUITRY
VR_RDY Signal
The VR_RDY pin is an open-drain logic output which
indicates that the soft-start period has completed and the
output voltage is within the regulated range. VR_RDY is
pulled low during shutdown and releases high after a
successful soft-start and a fixed delay t D5 . VR_RDY will be
pulled low when an undervoltage or overvoltage condition is
detected, or the controller is disabled by a reset from
EN_PWR, EN_VTT, POR, or VID OFF-code.
Undervoltage Detection
The undervoltage threshold is set at 50% of the VID code.
When the output voltage at VSEN is below the undervoltage
threshold, VR_RDY is pulled low.
Overvoltage Protection
Regardless of the VR being enabled or not, the ISL6334B,
ISL6334C overvoltage protection (OVP) circuit will be active
after its POR. The OVP thresholds are different under different
operation conditions. When VR is not enabled and during the
soft-start intervals t D1 , t D2 and t D3 , the OVP threshold is
1.273V. Once the controller detects valid VID input, the OVP
trip point will be changed to DAC plus 175mV.
Two actions are taken by ISL6334B, ISL6334C to protect the
microprocessor load when an overvoltage condition occurs.
At the inception of an overvoltage event, all PWM outputs are
commanded low instantly (less than 20ns). This causes the
Intersil drivers to turn on the lower MOSFETs and pull the
output voltage below a level to avoid damaging the load. When
the VDIFF voltage falls below the DAC plus 75mV, PWM
signals enter a high-impedance state. The Intersil drivers
respond to the high-impedance input by turning off both upper
FN6689.2
August 31, 2010
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| ISL6334CCRZ | 功能描述:IC CTRLR PWM SYNC BUCK 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6334CCRZ-T | 功能描述:IC CTRLR PWM SYNC BUCK 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6334CIRZ | 功能描述:IC CTRLR PWM SYNC BUCK 40-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:2,000 系列:- 应用:控制器，DSP 输入电压:4.5 V ~ 25 V 输出数:2 输出电压:最低可调至 1.2V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:30-TFSOP（0.173"，4.40mm 宽） 供应商设备封装:30-TSSOP 包装:带卷 (TR) |
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