参数资料
| 型号： | ISL6422BEVEZ-T |
| 厂商： | Intersil |
| 文件页数： | 12/18页 |
| 文件大小： | 0K |
| 描述： | IC VREG DUAL LNB W/I2C 38EPTSSOP |
| 标准包装： | 2,500 |
| 应用： | 转换器，卫星信号接收机顶盒设计 |
| 输入电压： | 8 V ~ 14 V |
| 输出数： | 2 |
| 输出电压： | 13.3 V ~ 18.3 V，14.3 V ~ 19.3 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 38-TFSOP （0.173"，4.40mm 宽）裸露焊盘 |
| 供应商设备封装： | 38-TSSOP 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6422B
The STOP condition is a LOW to HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent
before each START condition.
SDA
ISL6422B Software Description
Interface Protocol
The interface protocol is comprised of the following, as
shown below in Table 2:
? A start condition (S)
? A chip address byte (MSB on left; the LSB bit determines
read (1) or write (0) transmission) (the assigned I 2 C slave
SCL
S
START
P
STOP
address for the ISL6422B is 0001 00XX)
? A sequence of data (1 byte + Acknowledge)
CONDITION CONDITION
FIGURE 5. START AND STOP WAVEFORMS
? A stop condition (P)
TABLE 2. INTERFACE PROTOCOL
Byte Format
S 0
0
0
1
0
0
0 R/W ACK
Data (8 bits)
ACK P
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
Acknowledge
System Register Format
? R, W = Read and Write bit
? R = Read-only bit
All bits reset to 0 at Power-On
TABLE 3. STATUS REGISTER 1 (SR1)
The master (microprocessor) puts a resistive HIGH level on
R, W
R, W
R, W
R
R
R
R
R
the SDA line during the acknowledge clock pulse (Figure 6).
SR1H
SR1M
SR1L
OTF
CABF1 OUVF1 OLF1
BCF1
The peripheral that acknowledges has to pull-down (LOW)
the SDA line during the acknowledge clock pulse so that the
TABLE 4. TONE REGISTER 2 (SR2)
SDA line is stable LOW during this clock pulse (of course,
R, W
R, W
R, W
R, W
R, W
R, W
R, W
R, W
set-up and hold times must also be taken into account).
SR2H
SR2M
SR2L
ENT1
MSEL1 TTH1
X
X
The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
TABLE 5. COMMAND REGISTER 3 (SR3)
the SDA line remains at the HIGH level during the ninth
R, W
R, W
R, W
R, W
R, W
R, W
R, W
R, W
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
SR3H SR3M SR3L
DCL1 VSPEN1 ISEL1R ISEL1H ISEL1L
The ISL6422B will not generate the acknowledge if the
TABLE 6. CONTROL REGISTER 4 (SR4)
POWER OK signal from the UVLO is LOW.
R, W
R, W
R, W
R, W
R, W
R, W
R, W
R, W
SCL
SR4H
SR4M
SR4L
EN1
X
X
VTOP1 VBOT1
1
2
8
9
TABLE 7. STATUS REGISTER 5 (SR5)
SDA
R, W
R, W
R, W
X
R
R
R
R
MSB
SR5H
SR5M
SR5L
X
CABF2 OUVF2 OLF2
BCF2
START
ACKNOWLEDGE
FROM SLAVE
TABLE 8. TONE REGISTER 6 (SR6)
FIGURE 6. ACKNOWLEDGE ON THE I 2 C BUS
R, W
R, W
R, W
R, W
R, W
R, W
R, W
R, W
SR6H
SR6M
SR6L
ENT2 MSEL2 TTH2
X
X
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the
TABLE 9. COMMAND REGISTER 7 (SR7)
microprocessor can use a simpler transmission; it waits one
R, W
R, W
R, W
R, W
R, W
R, W
R, W
R, W
clock without checking the slave acknowledging, and sends
the new data. Although, this approach is less protected from
SR7H SR7M SR7L
DCL2 VSPEN2 ISEL2R ISEL2H ISEL2L
error and decreases the noise immunity.
TABLE 10. CONTROL REGISTER 8 (SR8)
R, W
R, W
R, W
R, W
R, W
R, W
R, W
R, W
SR8H
SR8M
SR8L
EN2
X
X
VTOP2 VBOT2
NOTE: X = Bit not used
12
FN6486.1
August 10, 2007
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| ISL6422ERZ | 功能描述:电流型 PWM 控制器 DL LNB SUPPLY + CONT VAGEG W/I2C RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6422ERZ-T | 功能描述:电流型 PWM 控制器 DL LNB SUPPLY + CONT VAGEG W/I2C RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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