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| 型号： | ISL6442IAZ |
| 厂商： | Intersil |
| 文件页数： | 10/16页 |
| 文件大小： | 0K |
| 描述： | IC REG TRPL BCK/LINEAR 24QSOP |
| 标准包装： | 1,000 |
| 拓扑： | 降压（降压）同步（2），线性（LDO）（1） |
| 功能： | 任何功能 |
| 输出数： | 3 |
| 频率 - 开关： | 300kHz ~ 2.55MHz |
| 电压/电流 - 输出 1： | 控制器 |
| 电压/电流 - 输出 2： | 控制器 |
| 电压/电流 - 输出 3： | 控制器 |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 无 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | 24-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | * |
| 包装： | 管件 |
ISL6442
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
soft-start ramp, and it does NOT shut off, unless VCC goes
back below the falling POR trip point. It is suggested that using
one of the switcher outputs as the input to the linear allows it to
be ramped and enabled/disabled with that switcher.
Protection Mechanisms
OCP - (Function independent for both PWM). The overcurrent
function protects the PWM Converter from a shorted output by
using the upper MOSFET’s ON-resistance, r DS(ON) to monitor
the current. This method enhances the converter’s efficiency
and reduces cost by eliminating a current sensing resistor. The
overcurrent function cycles the soft-start function in a hiccup
0.0
0
5 10 15 20 25 30 35
RT (k Ω )
FIGURE 10. FREQUENCY vs RT RESISTOR
40
mode to provide fault protection. A resistor connected to the
drain of the upper MOSFET and OCSET pin programs the
overcurrent trip level. The PHASE node voltage will be
compared against the voltage on the OCSET pin, while the
Output Regulation
Figure 11 shows the generic feedback resistor circuit for any
of the three V OUT ’s; the V OUT is divided down to equal the
reference. All three use a 0.6V internal reference (check the
“Electrical Specifications” Table on page 4 for the exact
reference value at 24V). The R UP is connected to the V OUT ;
the R LOW to GND; the common point goes to the FB pin.
upper MOSFET is on. A current (typically 110μA) is pulled from
the OCSET pin to establish the OCSET voltage. If PHASE is
lower than OCSET while the upper MOSFET is on then an
overcurrent condition is detected for that clock cycle. The upper
gate pulse is immediately terminated, and a counter is
incremented. If an overcurrent condition is detected for 32
consecutive clock cycles, and the circuit is not in soft-start, the
ISL6442 enters into the soft-start hiccup mode. During hiccup,
V OUT
R UP
FB
EA
COMP
the external capacitor on the SS/EN pin is discharged, then
released and a soft-start cycle is initiated. During soft-start,
pulse termination current limiting is enabled, but the 32-cycle
R LOW
0.6V
FIGURE 11. OUTPUT REGULATION
V OUT must be greater than 0.6V and 2 resistors are needed,
and their accuracy directly affect the regulator tolerance.
hiccup counter is held in reset until soft-start is completed.
Figure 12 shows an example of the hiccup mode. As the
SS2/EN2 is pulled below the enable trip point, VOUT2 shuts
off, and the voltage goes to GND, at which time the output
current goes to zero. As SS2/EN2 rises above the enable
trip point, the output tries to turn on, the current spikes up,
and then is held constant (by the pulse-termination current
FB = V OUT ? -----------------------------------
R + R
R LOW
UP LOW
(EQ. 4)
limiting); the output voltage rises, but not up to the desired
value. When the SS2/EN2 ramp reaches ~3V, the cycle
repeats, and can continue indefinitely. If the short-circuit is
Use Equation 5 to choose the resistor values. R UP is part of
the compensation network for the switchers, and should be
selected to be compatible; 1k Ω to 5k Ω is a good starting
value. Find FB from the “Electrical Specifications” Table on
page 5 (for the right condition), plug in the desired value for
V OUT , and solve for R LOW .
removed, the output will ramp up with the next soft-start, and
normal operation will resume. VOUT1 and SS1/EN1 will
independently function the same way.
GND>
R LOW = ------------------------------
FB ? R UP
V OUT – FB
(EQ. 5)
VOUT2 (2V/DIV)
The maximum duty cycle of the ISL6442 approaches 100%
at low frequency, but falls off at higher frequency; see the
“Electrical Specifications” Table on page 5. In addition, there
is a minimum UGATE pulse width, in order to properly sense
overcurrent. The two switchers are 180° out of phase.
The linear output voltage is restricted to approximately a 1V to
4V range. VIN3 should be equal or less than VCC (in order to
0A>
I OUT2 (2A/DIV)
be sure that LCDR can turn off the PNP). Note that the linear
output is off until the rising POR trips; it does not have a
10
GND>
SS2/EN2 (1V/DIV)
FIGURE 12. OVERCURRENT PROTECTION
FN9204.2
October 31, 2008
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