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| 型号： | ISL6442IAZ |
| 厂商： | Intersil |
| 文件页数： | 9/16页 |
| 文件大小： | 0K |
| 描述： | IC REG TRPL BCK/LINEAR 24QSOP |
| 标准包装： | 1,000 |
| 拓扑： | 降压（降压）同步（2），线性（LDO）（1） |
| 功能： | 任何功能 |
| 输出数： | 3 |
| 频率 - 开关： | 300kHz ~ 2.55MHz |
| 电压/电流 - 输出 1： | 控制器 |
| 电压/电流 - 输出 2： | 控制器 |
| 电压/电流 - 输出 3： | 控制器 |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 无 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | 24-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | * |
| 包装： | 管件 |
ISL6442
Figure 8 shows pre-biased outputs before soft-start. The
solid blue curve shows no pre-bias; the output starts ramping
all 3 outputs are within their expected ranges, the PGOOD
will start an internal timer, with Equation 3:
t PGOOD = ------------------
from GND. The magenta dotted line shows the output
pre-biased to a voltage less than the final output. The FETs
0.5236
F SW
(EQ. 3)
don’t turn on until the soft-start ramp voltage exceeds the
output voltage; then the output starts ramping seamlessly
from there. The cyan dotted line shows the output pre-
biased above the final output (but below the OVP
(Overvoltage Protection)). The FETs will not turn on until the
end of the soft-start ramp; then the output will be quickly
pulled down to the final value.
If the output is pre-biased above the OVP level, the ISL6442
will go into OVP at the end of soft-start, which will keep the
FETs off. The output can recover if the voltage goes below the
UV (Undervoltage) trip point, at which time a retry will occur. If
successful, the output will ramp back up to the normal level.
VOUT1 has the same functionality as previously described
for VOUT2. Each output should react independently of the
other, unless they are related by the circuit configuration.
where:
t PGOOD is the delay time (in sec)
F SW is the switching frequency (in MHz)
Once the time-out is complete, the internal pull-down device
will shut off, allowing the open-drain PGOOD output to rise
through an external pull-up resistor, to a 5V (or lower) supply,
which signals that the “Power is GOOD”. Figure 9 shows the
three outputs turning on, and the delay for PGOOD. If any of
the conditions is subsequently violated, then PGOOD goes
low. Once the voltage returns to the normal region, a new
delay will start, after which the PGOOD will go high again.
The PGOOD delay is inversely proportional to the clock
frequency. If the clock is running as slow as 524kHz, the
delay will be one second long. There is no way to adjust the
PGOOD delay independently of the clock.
SS2/EN2 (0.5V/DIV)
PGOOD (5V/DIV)
GND>
VOUT2 OVER-CHARGED
VOUT2 (2V/DIV)
GND>
VOUT3 (2V/DIV)
V OUT2 (2V/DIV )
VOUT2 PRE-BIASED
GND>
GND>
VOUT1 (2V/DIV)
GND>
FIGURE 8. SOFT-START WITH PRE-BIAS
NOTE: Neither output cannot be independently disabled during
power-up; both SS/EN pins are pulled low internally during POR, and
due to the internal switch, neither will start charging if either pin is still
held low. Once the outputs are running, either output can be disabled
and then enabled again, without affecting the other one that’s
running. But if both SS/EN pins are held low at the same time, then
the internal switch will turn on, and both SS/EN pins must be released
before they both start to ramp.
The linear output does not have a soft-start ramp; however, it
may follow the ramp of its input supply, if timed to coincide
with its rise, after the VCC rising POR trip. If the input to the
linear is from one of the two switcher outputs, then it will
share the same ramp rate as the switcher.
PGOOD
A group of comparators (separate from the protection
comparators) monitor the output voltages (via the FB pins)
for PGOOD. Each switcher has an lower and upper
boundary (nominally around 90% and 110% of the target
value) and the linear has a lower boundary (around 75% of
the target). Once both switcher output ramps are done, and
9
FIGURE 9. PGOOD DELAY
Monotonic Output
During soft-start period, the low side MOSFET is disabled to
achieve monotonic output voltage when the inductor current
is negative. This also allows ramping up into a pre-charged
output voltage.
Switching Frequency
The switching frequency of the ISL6442 is determined by the
external resistor placed from the RT pin to SGND. See
Figure 10 for a graph of Frequency versus RT Resistance.
The “Electrical Specifications” Table on page 5 lists a low
end value of 52.3k Ω for 300kHz operation (not shown on
graph). Running at both high frequency and high VIN
voltages is not recommended, due to the increased power
dissipation on-chip (mostly from the internal VCC regulator,
which supplies gate drivers). The user should check the
maximum acceptable IC temperature, based on their
particular conditions.
FN9204.2
October 31, 2008
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