参数资料
型号: ISL6442IAZ
厂商: Intersil
文件页数: 15/16页
文件大小: 0K
描述: IC REG TRPL BCK/LINEAR 24QSOP
标准包装: 1,000
拓扑: 降压(降压)同步(2),线性(LDO)(1)
功能: 任何功能
输出数: 3
频率 - 开关: 300kHz ~ 2.55MHz
电压/电流 - 输出 1: 控制器
电压/电流 - 输出 2: 控制器
电压/电流 - 输出 3: 控制器
带 LED 驱动器:
带监控器:
带序列发生器:
电源电压: 4.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: *
封装/外壳: 24-SSOP(0.154",3.90mm 宽)
供应商设备封装: *
包装: 管件
ISL6442
LCDR
R307
R300
Q300
VIN3
C IN3
ISL6442
V IN
C300
LCFB
R301
V OUT3
UGATE
Q1
L OUT
V OUT
R302
C OUT3
PHASE
LGATE
Q2
C IN
C OUT
PGND
FIGURE 16. LINEAR COMPENSATION COMPONENTS
Strategy
1. The output capacitor of the linear regulator circuit must be
chosen such that the ESR Zero is less than 200kHz:
RETURN
FIGURE 17. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
F Z1 < 200kHz
(EQ. 30)
2. The voltage divider can be chosen to sink 250μA to
1.5mA of sense current, but this is simply a guideline, not
V OUT3 – 0.6V
R301 = --------------------------------------
(EQ. 32)
R302 = ------------
SS
a rule. The values should be chosen such that
(EQ. 31)
I sen
0.6V
I sen
where I sen = is the current through the resistor divider,
and 0.6V is the internal voltage reference that LCFB will
C VCC
VCC
BOOT
ISL6442
PHASE
RT
VIN
C BOOT C IN
+V IN
+V IN
Q1 L OUT
Q2 C OUT
V OUT
equal.
SGND PGND
3. Compute the pole and zero for the linear regulator circuit
from Equations 31 and 32.
4. Make:
R RT C SS
SGND
C VIN
PGND
F P2 = ----------
F Z1
10
(EQ. 33)
FIGURE 18. PRINTED CIRCUIT BOARD POWER AND
5. Fix R300 at 100 Ω . Solve for C300. Use an MLCC, COG
or NPO type capacitor for this value.
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible using ground
plane construction or single point grounding.
Figure 17 shows the critical power components of the
converter. To minimize the voltage overshoot, the
interconnecting wires indicated by heavy lines should be part
of ground or power plane in a printed circuit board. The
components shown in Figure 17 should be located as close
together as possible. Please note that the capacitors C IN
and C OUT each represent numerous physical capacitors.
Locate the ISL6442 within 1 inch of the MOSFETs, Q1 and
Q2. The circuit traces for the MOSFETs’ gate and source
connections from the ISL6442 must be sized to handle up to
2A peak current.
15
GROUND PLANES OR ISLANDS
Figure 18 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Locate the RT resistor as
close as possible to the RT pin and the SGND pin. Provide
local decoupling between VCC and GND pins.
For each switcher, minimize any leakage current paths on
the SS/EN pin and locate the capacitor, C SS close to the
SS/EN pin because the internal current source is only 30μA.
All of the compensation network components for each
switcher should be located near the associated COMP and
FB pins. Locate the capacitor, C BOOT as close as practical
to the BOOT and PHASE pins (but keep the noisy PHASE
plane away from the IC (except for the PHASE pin
connection).
The OCSET circuits (see Figure 2) should have a separate
trace from the upper FET to the OCSET R and C; that will
more accurately sense the VIN at the FET than just tying
them to the VIN plane. The OCSET R and C should be
placed near the IC pins.
FN9204.2
October 31, 2008
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