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| 型号： | ISL6504CBZ-T |
| 厂商： | Intersil |
| 文件页数： | 8/16页 |
| 文件大小： | 0K |
| 描述： | IC PWR SUPPLY CTRLR/MONTR 16SOIC |
| 标准包装： | 1,000 |
| 应用： | 电源控制器/监控器 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 电流 - 电源： | 17mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
ISL6504, ISL6504A
well as all the control and monitoring functions necessary for
complete ACPI implementation.
Initialization
The ISL6504/A automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continually
monitors the 5V SB input supply voltage, initiating
3.3V DUAL /3.3V SB and 1.5V SB soft-start operation shortly
after exceeding POR threshold.
Dual Outputs Operational Truth Table
Table 1 describes the truth combinations pertaining to the
3.3V DUAL/SB and 5V DUAL outputs. The last two lines
highlight the only difference between the ISL6504 and
ISL6504A. The internal circuitry does not allow the transition
from an S3 (suspend to RAM) state to an S4/S5 (suspend to
disk/soft off) state or vice versa. The only ‘legal’ transitions
are from an active state (S0, S1) to a sleep state (S3, S5)
and vice versa.
TABLE 1. 5V DUAL OUTPUT (V OUT4 ) TRUTH TABLE
5VSB
S3
S5
3.3V, 5V
3V3DLSB
DLA
3V3DL
5VDLSB
5VDL
FIGURE 4. 5V DUAL AND 3.3V DUAL /3.3V SB TIMING
DIAGRAM; ISL6504
S5
S3
3.3VDL/SB
5VDL
COMMENTS
1
1
0
0
0
1
0
1
0
0
3.3V
3.3V
3.3V
3.3V
Note
5V
5V
0V
5V
S0/S1/S2 States (Active)
S3
Maintains Previous State
S4/S5 (ISL6504)
S4/S5 (ISL6504A)
5VSB
S3
S5
3.3V, 5V
NOTE: Combination Not Allowed.
Functional Timing Diagrams
Figures 4 (ISL6504), 5 (ISL6504A), and 6 are timing diagrams,
detailing the power up/down sequences of all the outputs in
response to the status of the sleep-state pins (S3, S5), as well
as the status of the input ATX supply. Not shown in these
diagrams is the deglitching feature used to protect against false
sleep state tripping. Both S3 and S5 pins are protected against
noise by a 2 μ s filter (typically 1–4 μ s). This feature is useful in
noisy computer environments if the control signals have to
travel over significant distances. Additionally, the S3 pin
features a 200 μ s delay in transitioning to sleep states. Once the
S3 pin goes low, an internal timer is activated. At the end of
the 200 μ s interval, if the S5 pin is low, the ISL6504/A
switches into S5 sleep state; if the S5 pin is high, the
ISL6504/A goes into S3 sleep state.
8
3V3DLSB
DLA
3V3DL
5VDLSB
5VDL
FIGURE 5. 5V DUAL AND 3.3V DUAL /3.3V SB TIMING
DIAGRAM; ISL6504A
5VSB
S3
S5
3.3V,
5V, 12V
DLA
1V5SB
1V2VID
FIGURE 6. 1.5V SB , AND 1.2V VID TIMING DIAGRAM
FN9062.2
April 13, 2004
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6504CR | 功能描述:IC MULTIPLE POWER CTRLR 20-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 电源控制器，监视器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 应用:多相控制器 输入电压:- 电源电压:9 V ~ 14 V 电流 - 电源:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（5x5） 包装:带卷 (TR) |
| ISL6504CR-T | 功能描述:IC MULTIPLE POWER CTRLR 20-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 电源控制器，监视器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 应用:多相控制器 输入电压:- 电源电压:9 V ~ 14 V 电流 - 电源:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（5x5） 包装:带卷 (TR) |
| ISL6505 WAF | 制造商:Intersil Corporation 功能描述: |
| ISL6505C WAF | 制造商:Intersil Corporation 功能描述: |
| ISL6505CB | 功能描述:IC MULTIPLE POWER CTRLR 20-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 电源控制器，监视器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 应用:多相控制器 输入电压:- 电源电压:9 V ~ 14 V 电流 - 电源:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:40-WFQFN 裸露焊盘 供应商设备封装:40-TQFN-EP（5x5） 包装:带卷 (TR) |
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