参数资料
型号: ISL6524ACB
厂商: Intersil
文件页数: 12/16页
文件大小: 0K
描述: IC CTRLR VRM8.5 PWM TRPL 28-SOIC
标准包装: 26
应用: 控制器,Intel VRM8.5
输入电压: 10.8 V ~ 13.2 V
输出数: 4
输出电压: 多重
工作温度: 0°C ~ 70°C
安装类型: *
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: *
包装: 管件
Compensation Break Frequency Equations
PWM Output Capacitors
F Z1 = -----------------------------------
F P1 = -------------------------------------------------------
2 π × R 2 × ? ---------------------- ?
F Z2 = -------------------------------------------------------
F P2 = -----------------------------------
1
2 π × R 2 × C1
1
2 π × ( R1 + R3 ) × C3
1
C1 × C2
? C1 + C2 ?
1
2 π × R 3 × C3
Modern microprocessors produce transient load rates
above 1A/ns. High frequency capacitors initially supply the
transient current and slow the load rate-of-change seen by
the bulk capacitors. The bulk filter capacitor values are
generally determined by the ESR (effective series
Figure 12 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown in Figure 12. Using the above guidelines
should yield a Compensation Gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F P2 with the capabilities
of the error amplifier. The Closed Loop Gain is constructed on
the log-log graph of Figure 12 by adding the Modulator Gain (in
dB) to the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the compensation
transfer function and plotting the gain.
resistance) and voltage rating requirements rather than
actual capacitance requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple voltage and
100
F Z 1
F Z2
F P1
F P2
OPEN LOOP
ERROR AMP GAIN
the initial voltage drop following a high slew-rate transient’s
edge. An aluminum electrolytic capacitor’s ESR value is
? V IN ?
80
60
40
20
20 log ? ------------------ ?
? V P – P ?
COMPENSATION
GAIN
related to the case size with lower ESR available in larger
case sizes. However, the equivalent series inductance (ESL)
of these capacitors increases with case size and can reduce
the usefulness of the capacitor to high slew-rate transient
loading. Unfortunately, ESL is not a specified parameter. Work
with your capacitor supplier and measure the capacitor’s
20 log ? -------- ?
0
-20
-40
R2
? R1 ?
MODULATOR
GAIN
F LC
F ESR
CLOSED LOOP
GAIN
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Linear Output Capacitors
-60
10
100
1K
10K 100K
FREQUENCY (Hz)
1M
10M
The output capacitors for the linear regulators provide
dynamic load current. Thus capacitors C OUT2 , C OUT3 , and
C OUT4 should be selected for transient load regulation.
FIGURE 12. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation gain uses external impedance networks
Z FB and Z IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than
45 degrees. Include worst case component variations when
determining phase margin.
Component Selection Guidelines
PWM Output Inductor Selection
The PWM converter requires an output inductor. The output
inductor is selected to meet the output voltage ripple
requirements and sets the converter ’s response time to a
load transient. The inductor value determines the converter ’s
ripple current and the ripple voltage is a function of the ripple
current. The ripple voltage and current are approximated by
the following equations:
V IN – V OUT V OUT
F S × L
Output Capacitor Selection
The output capacitors for each output have unique
? I = -------------------------------- × ----------------
V IN
? V OUT = ? I × ESR
requirements. In general the output capacitors should be
selected to meet the dynamic regulation requirements.
Additionally, the PWM converter requires an output capacitor
to filter the current ripple. The load transient for the
microprocessor core requires high quality capacitors to
supply the high slew rate (di/dt) current demands.
12
Increasing the value of inductance reduces the ripple current
and voltage. However, large inductance values increase the
converter ’s response time to a load transient.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6524A will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
FN9064.1
April 8, 2005
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