参数资料
| 型号： | ISL6524ACB |
| 厂商： | Intersil |
| 文件页数： | 9/16页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR VRM8.5 PWM TRPL 28-SOIC |
| 标准包装： | 26 |
| 应用： | 控制器，Intel VRM8.5 |
| 输入电压： | 10.8 V ~ 13.2 V |
| 输出数： | 4 |
| 输出电压： | 多重 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | * |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | * |
| 包装： | 管件 |
I PEAK = ----------------------------------------------------
current increases through the inductor (L OUT1 ). At time T1,
the OC1 comparator trips when the voltage across Q1 (i D ?
r DS(ON) ) exceeds the level programmed by R OCSET . This
inhibits outputs 1, 2, and 3, discharges the soft-start capacitor
C SS24 with 28 μ A current sink, and increments the counter.
Soft-start capacitor C SS13 is quickly discharged. C SS13 starts
ramping up at T2 and initiates a new soft-start cycle. With
OUT2 still overloaded, the inductor current increases to trip
the over-current comparator. Again, this inhibits the outputs,
but the C SS24 soft-start voltage continues increasing to above
4.0V before discharging. Soft-start capacitor C SS13 is, again,
quickly discharged. The counter increments to 2. The soft-
start cycle repeats at T3 and trips the over-current
comparator. The SS24 pin voltage increases to above 4.0V at
T4 and the counter increments to 3. This sets the fault latch to
disable the converter.
across R OCSET helps V OCSET track the variations of V IN due
to MOSFET switching. The over-current function will trip at a
peak inductor current (I PEAK) determined by:
I OCSET × R OCSET
r DS ( ON )
The OC trip point varies with MOSFET’s rDS(ON)
temperature variations. To avoid over-current tripping in the
normal operating load range, determine the ROCSET
resistor value from the equation above with:
1. The maximum r DS(ON) at the highest junction temperature
2. The minimum I OCSET from the specification table
3. Determine I PEAK for I PEAK > I OUT(MAX) + ( ? I) / 2,
where ? I is the output inductor ripple current.
For an equation for the ripple current see the section under
component guidelines titled ‘Output Inductor Selection’.
10V
FAULT
REPORTED
OVER-CURRENT TRIP:
V IN = +5V
0V
COUNT
=1
COUNT
=2
COUNT
=3
i
D
V DS > V SET
× r DS ( ON ) > I OCSET × R OCSET
OCSET
R OCSET
4V
2V
I OCSET
200 μ A
V SE T +
i D
VCC
0V
DRIVE
UGATE
+
OVERLOAD
APPLIED
OC
+
-
PHASE
V DS
0A
PWM
GATE
CONTROL
V PHASE = V IN – V DS
V OCSET = V IN – V SET
T0 T1
T2
TIME
T3 T4
FIGURE 9. OVER-CURRENT DETECTION
FIGURE 8. OVER-CURRENT OPERATION
The three linear controllers monitor their respective VSEN
pins for under-voltage. Should excessive currents cause
VSEN3 or VSEN4 to fall below the linear under-voltage
threshold, the respective UV signals set the OC latch or the
FAULT latch, providing respective C SS capacitors are fully
charged. Blanking the UV signals during the C SS charge
interval allows the linear outputs to build above the under-
voltage threshold during normal operation. Cycling the bias
input power off then on resets the counter and the fault latch.
An external resistor (R OCSET ) programs the over-current trip
level for the PWM converter. As shown in Figure 9, the internal
200 μ A current sink (I OCSET ) develops a voltage across
R OCSET (V SET ) that is referenced to V IN . The DRIVE signal
enables the over-current comparator (OC). When the voltage
across the upper MOSFET (V DS(ON) ) exceeds V SET , the over-
current comparator trips to set the over-current latch. Both
V SET and V DS are referenced to V IN and a small capacitor
9
OUT1 Voltage Program
The output voltage of the PWM converter is programmed to
discrete levels between 1.050V and 1.825V. This output
(OUT1) is designed to supply the core voltage of Intel’s
advanced microprocessors. The voltage identification (VID)
pins program an internal voltage reference (DACOUT) with a
TTL-compatible 5-bit digital-to-analog converter (DAC). The
level of DACOUT also sets the PGOOD and OVP thresholds.
Table 1 specifies the DACOUT voltage for the different
combinations of connections on the VID pins. The VID pins
can be left open for a logic 1 input, since they are internally
pulled to the VAUX pin through 5k ? resistors. Changing the
VID inputs during operation is not recommended and could
toggle the PGOOD signal and exercise the over-voltage
protection. The output voltage program is Intel VRM8.5
compatible.
FN9064.1
April 8, 2005
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| ISL6524ACBZ | 功能描述:IC CTRLR VRM8.5 PWM TRPL 28-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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| ISL6524ACBZ-T | 功能描述:IC CTRLR VRM8.5 PWM TRPL 28-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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