参数资料
型号: ISL6524CBZ
厂商: Intersil
文件页数: 11/16页
文件大小: 0K
描述: IC CTLR VRM8.5 PWM TRPL 28-SOIC
标准包装: 26
应用: 控制器,Intel VRM8.5
输入电压: 10.8 V ~ 13.2 V
输出数: 4
输出电压: 多重
工作温度: 0°C ~ 70°C
安装类型: *
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: *
包装: 管件
产品目录页面: 1244 (CN2011-ZH PDF)
Dedicate another solid layer as a power plane and break this
plane into smaller islands of common voltage levels. The
power plane should support the input power and output
power nodes. Use copper filled polygons on the top and
bottom circuit layers for the PHASE node, but do not
unnecessarily oversize this particular island. Since the
The modulator transfer function is the small-signal transfer
function of V OUT /V E/A . This function is dominated by a DC
Gain, given by V IN /V OSC , and shaped by the output filter, with
a double pole break frequency at F LC and a zero at F ESR .
V IN
PHASE node is subject to very high dV/dt voltages, the stray
OSC
DRIVER
-
capacitor formed between these island and the surrounding
circuitry will tend to couple switching noise. Use the
remaining printed circuit layers for small signal wiring. The
wiring traces from the control IC to the MOSFET gate and
? V OSC
PWM
COMP
+
DRIVER
L O
PHASE
C O
V OUT
source should be sized to carry 2A peak currents.
ESR
+5V IN
L IN
V E/A
Z FB
(PARASITIC)
ERROR
V OUT
Z IN
+3.3V IN
V OUT2
C IN
Q3
+12V
C VCC
VCC GND
DRIVE2
OCSET
UGATE
C OCSET
R OCSET
Q1
L OUT
V OUT1
- Z IN
+
REFERENCE
AMP
DETAILED COMPENSATION COMPONENTS
Z FB
C2
C OUT2
PHASE
C1
R2
C3
R3
SS24
LGATE
Q2
C OUT1
CR1
COMP
R1
V OUT3
C SS24,13
C OUT3
SS13
ISL6524
DRIVE3 DRIVE4
C OUT4
V OUT4
ISL6524
-
+
DACOUT
FB
+3.3V IN
KEY
Q4
PGND
Q5
FIGURE 11. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
Modulator Break Frequency Equations
F LC = ----------------------------------------
F ESR = -----------------------------------------
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA/THROUGH-HOLE CONNECTION TO GROUND PLANE
1
2 π × L O × C O
1
2 π × ESR × C O
FIGURE 10. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
PWM1 Controller Feedback Compensation
The PWM controller uses voltage-mode control for output
regulation. This section highlights the design consideration for a
voltage-mode controller requiring external compensation.
Figure 11 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V OUT ) is regulated to the Reference voltage level. The
reference voltage level is the DAC output voltage (DACOUT)
for the PWM. The error amplifier output (V E/A ) is compared with
the oscillator (OSC) triangular wave to provide a pulse-width
modulated wave with an amplitude of V IN at the PHASE node.
The PWM wave is smoothed by the output filter (L O and C O ).
11
The compensation network consists of the error amplifier
(internal to the ISL6524) and the impedance networks Z IN and
Z FB . The goal of the compensation network is to provide a
closed loop transfer function with high 0dB crossing frequency
(f 0dB ) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f 0dB and 180 o .
The equations below relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 11. Use these guidelines for locating the poles
and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1 ST Zero Below Filter’s Double Pole (~75% F LC )
3. Place 2 ND Zero at Filter’s Double Pole
4. Place 1 ST Pole at the ESR Zero
5. Place 2 ND Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
FN9015.3
April 18, 2005
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