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参数资料
| 型号： | ISL6524CBZ |
| 厂商： | Intersil |
| 文件页数： | 9/16页 |
| 文件大小： | 0K |
| 描述： | IC CTLR VRM8.5 PWM TRPL 28-SOIC |
| 标准包装： | 26 |
| 应用： | 控制器，Intel VRM8.5 |
| 输入电压： | 10.8 V ~ 13.2 V |
| 输出数： | 4 |
| 输出电压： | 多重 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | * |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | * |
| 包装： | 管件 |
| 产品目录页面： | 1244 (CN2011-ZH PDF) |
4.0V before discharging. Soft-start capacitor C SS13 is, again,
quickly discharged. The counter increments to 2. The soft-
start cycle repeats at T3 and trips the overcurrent comparator.
The SS24 pin voltage increases to above 4.0V at T4 and the
counter increments to 3. This sets the fault latch to disable the
converter.
The OC trip point varies with MOSFET’s r DS(ON)
temperature variations. To avoid overcurrent tripping in the
normal operating load range, determine the ROCSET
resistor value from the equation above with:
1. The maximum r DS(ON) at the highest junction temperature
2. The minimum I OCSET from the specification table
10V
0V
FAULT
REPORTED
3. Determine I PEAK for I PEAK > I OUT(MAX) + (DI) / 2,
where DI is the output inductor ripple current.
For an equation for the ripple current see the section under
COUNT
=1
COUNT
=2
COUNT
=3
component guidelines titled ‘Output Inductor Selection’.
DS
SET
4V
2V
0V
OVERLOAD
APPLIED
i
D
OVERCURRENT TRIP:
V > V
× r DS ( ON ) > I OCSET × R OCSET
OCSET
I OCSET
200 μ A
R OCSET
V SE T +
V IN = +5V
i D
VCC
DRIVE
UGATE
+
V DS
0A
T0 T1 T2 T3 T4
TIME
FIGURE 8. OVERCURRENT OPERATION
OC
PWM
+
-
GATE
CONTROL
PHASE
V PHASE = V IN – V DS
V OCSET = V IN – V SET
I PEAK = ----------------------------------------------------
The three linear controllers monitor their respective VSEN
pins for undervoltage. Should excessive currents cause
VSEN3 or VSEN4 to fall below the linear undervoltage
threshold, the respective UV signals set the OC latch or the
FAULT latch, providing respective C SS capacitors are fully
charged. Blanking the UV signals during the C SS charge
interval allows the linear outputs to build above the
undervoltage threshold during normal operation. Cycling the
bias input power off then on resets the counter and the fault
latch.
An external resistor (R OCSET ) programs the overcurrent trip
level for the PWM converter. As shown in Figure 9, the internal
200mA current sink (I OCSET ) develops a voltage across
R OCSET (V SET ) that is referenced to V IN . The DRIVE signal
enables the overcurrent comparator (OC). When the voltage
across the upper MOSFET (V DS(ON) ) exceeds V SET , the
overcurrent comparator trips to set the overcurrent latch. Both
V SET and V DS are referenced to V IN and a small capacitor
across R OCSET helps V OCSET track the variations of V IN due
to MOSFET switching. The overcurrent function will trip at a
peak inductor current (I PEAK) determined by:
I OCSET × R OCSET
r DS ( ON )
9
FIGURE 9. OVERCURRENT DETECTION
OUT1 Voltage Program
The output voltage of the PWM converter is programmed to
discrete levels between 1.050V and 1.825V. This output
(OUT1) is designed to supply the core voltage of Intel’s
advanced microprocessors. The voltage identification (VID)
pins program an internal voltage reference (DACOUT) with a
TTL-compatible 5-bit digital-to-analog converter (DAC). The
level of DACOUT also sets the PGOOD and OVP thresholds.
Table 1 specifies the DACOUT voltage for the different
combinations of connections on the VID pins. The VID pins
can be left open for a logic 1 input, since they are internally
pulled to the VAUX pin through 5kW resistors. Changing the
VID inputs during operation is not recommended and could
toggle the PGOOD signal and exercise the overvoltage
protection. The output voltage program is Intel VRM8.5
compatible.
FN9015.3
April 18, 2005
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