参数资料
型号: ISL6524EVAL1
厂商: Intersil
文件页数: 3/12页
文件大小: 0K
描述: EVALUATION BOARD VRM8.5 ISL6524
标准包装: 1
主要目的: 特殊用途 DC/DC,VRM 电源
输出及类型: 4,非隔离
输出电压: 1.05 ~ 1.825V,1.2V,1.5V,1.8V
电流 - 输出: 14A,1A,1A,1A
输入电压: 3.3V,5V,12V
稳压器拓扑结构: 降压
频率 - 开关: 200kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ISL6524
Application Note 9925
should yield a 1ms delay). At time T2, all conditions met,
PGOOD goes high.
3.3V IN
1.8V MCH
Note that the two power good pins are pulled high to VTT
and V CORE , respectively. If TTL compatibility is desired, feel
free to populate the provided spare footprints to ATX3.3V
level (while de-populating the default pull-up resistors).
Transient Response
For transient response testing, the evaluation boards were
1.2V VTT
V CORE
1.5V AGP
subjected to the loading presented in Table 2. Each output
response was recorded while the corresponding transient load
was applied. The results are presented in Figures 4 and 5.
GND>
TABLE 2. TRANSIENT OUTPUT LOADING DESCRIPTION
T0
T1
T2
2.5ms/DIV.
T3
T4
T5
OUTPUT
I OUT(MIN)
(A)
I OUT(MAX)
(A)
dI OUT /dt
(A/ μ s )
FREQUENCY
(Hz)
FIGURE 2. ISL6524EVAL1 START-UP
ISL6523EVAL1
V CORE
2.0
22.0
1.0
2500
Power Good Operation
(VOUT1)
The ISL6523 and ISL6524 output two PGOOD indicators
1.2VVTT
1.0
10.0
1.0
2000
(both open-collector outputs). VTTPG is maintained high
(VOUT2)
(pulled high by external pull-up resistor) as long as the
1.5VAGP
0.3
3.0
1.0
1500
1.2VVTT output exceeds 1.08V (90%; as sensed at the
(VOUT3)
VSEN pin). PGOOD is high for as long as V CORE is within
1.8VMCH
0.3
3.0
1.0
3000
power good limits (+/-10%), all linears are above their
undervoltage (UV) thresholds, and VTTPG is also high.
(VOUT4)
ISL6524EVAL1
V CORE
2.0
22.0
1.0
2500
(VOUT1)
1.2VVTT
0.5
6.0
1.0
2000
(VOUT2)
1.5VAGP
0.3
3.0
1.0
1500
1.8V MCH
(VOUT3)
V CORE
1.5V AGP
1.8VMCH
(VOUT4)
0.3
3.0
1.0
3000
NOTE: All transients 30% duty cycle.
1.2V VTT
GND>
VTTPG
2.5ms/DIV.
PGOOD
V CORE
T0
T1
T2
1.75V>
FIGURE 3. ISL6524EVAL1 POWER GOOD INDICATORS
1.20V>
1.2V VTT
Figure 3 details the operation of the power good functions.
Following the 1.2VVTT output rising above 1.08V at time T0,
VTTPG goes high simultaneously with enabling of the
V CORE regulator, approximately 4.5ms later. This timing
delay is given by the SS13 capacitor charging under a 28 μ A
constant current, to about 1.25V (bottom of internal oscillator
ramp). To reduce the delay, while preserving the same
1.50V>
1.80V>
1.5V AGP
1.8V MCH
ramping rate for the V CORE output, insert a resistor (footprint
provided; R18 and R22, respectively) of up to 100k ? in
series with the SS13 soft-start capacitor (100k ? resistor
3
100 μ s/DIV.
FIGURE 4. ISL6524EVAL1 OUTPUT TRANSIENT RESPONSE
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