参数资料
型号: ISL6524EVAL1
厂商: Intersil
文件页数: 5/12页
文件大小: 0K
描述: EVALUATION BOARD VRM8.5 ISL6524
标准包装: 1
主要目的: 特殊用途 DC/DC,VRM 电源
输出及类型: 4,非隔离
输出电压: 1.05 ~ 1.825V,1.2V,1.5V,1.8V
电流 - 输出: 14A,1A,1A,1A
输入电压: 3.3V,5V,12V
稳压器拓扑结构: 降压
频率 - 开关: 200kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ISL6524
Application Note 9925
Modifications
Adjusting the Output Voltage
All linear outputs controlled by the ISL6523 and ISL6524 are
adjustable by means of the resistive divider connecting the
VSEN pins to their respective outputs. If adjusting the output
voltage of the linear regulators, please pay attention to the
recommended resistor value selection guidelines described
in the data sheet. As the chips feature internal resistive
dividers that set the output voltages, in order to minimize DC
set-point interference with these resistors, it is
recommended the parallel combination of the external
resistive divider components be kept below 2k ? to 5k ? .
Furthermore, the ISL6524 has provisions (by grounding the
FIX pin) for bypassing the internal resistive dividers.
between two output voltage settings. The recommended
circuits for the dual processor GTL VTT and universal AGP
support implementation are shown in Figures 8 and 9. As
both the ISL6523 and ISL6524 were designed to regulate
the voltage present at the VSEN2 pin to 1.2V, the resistive
divider made out of Rs and Rp1 raise the DC regulation
setting of this output to 1.25V, while Qx is off. When Qx is
turned on (by means of a high TUAL5 signal), Rp2 is
connected in parallel to Rp1, raising the DC regulation
setting of this output to 1.5V.
+3.3VIN
V OUT3 (AGP)
DRIVE3
18
V OUT2 (VTT)
+1.25V / +1.5V
+
UGATE2
PHASE2
1
2
+1.5V / +3.3V
+
Rs
200 ?
VSEN3
Rp
162 ?
19
ISL6523/4
TO TYPEDET SIGNAL
Qx
Rs
200 ?
VSEN2
Rp2
953 ?
11
2N7002
FIGURE 9. ISL6523, ISL6524 UNIVERSAL AGP SUPPORT
IMPLEMENTATION
Rp1
TO TUAL5 SIGNAL
Qx
2N7002
4.75k ?
Same theory of operation applies to the circuit in Figure 9,
with the exception that while Qx is off (low TYPEDET signal)
the output is regulated to the internally-set 1.5V. A
TYPEDET high signal turns on Qx and raises the output
voltage to 3.3V. If AGP2X support is provided (3.3V output),
remember that for a low voltage drop across the pass
V OUT2 (VTT)
+1.25V / +1.5V
DRIVE2
1
element, a low r DS(ON) MOSFET needs to be selected (Q4
in circuit schematics).
Important to mention is the fact that for either regulator on
+
Rs
VSEN2
11
either IC, a sudden turn-on of Qx while the corresponding
output is within regulation may trigger an undervoltage
200 ?
and/or overcurrent event, resulting in a chip shutdown and
TO TUAL5 SIGNAL
Qx
2N7002
Rp2
953 ?
Rp1
4.75k ?
consequent re-start. If Qx is to be turned on while the
outputs are regulating, an RC low-pass network needs be
placed in series with its gate, in order to slow down its turn-
on (if a pull-up is used to generate the logic high signal, then
only the capacitor needs to be added). For this low-pass RC
network, a time constant of about 200-300 μ s is
recommended.
FIGURE 8. ISL6523, ISL6524 DUAL PROCESSOR GTL
IMPLEMENTATION
Recommended Implementation for Dual Processor
GTL VTT and Universal AGP Support
As both ICs have fixed output voltages, it is necessary to
implement an external circuit that helps switch a given output
5
Improving Output Voltage Tolerance
The key to improving the output voltage tolerance is
identifying the parameters which affect it, and then taking
steps toward improving them.
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