参数资料
型号: ISL6524EVAL1
厂商: Intersil
文件页数: 4/12页
文件大小: 0K
描述: EVALUATION BOARD VRM8.5 ISL6524
标准包装: 1
主要目的: 特殊用途 DC/DC,VRM 电源
输出及类型: 4,非隔离
输出电压: 1.05 ~ 1.825V,1.2V,1.5V,1.8V
电流 - 输出: 14A,1A,1A,1A
输入电压: 3.3V,5V,12V
稳压器拓扑结构: 降压
频率 - 开关: 200kHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ISL6524
Application Note 9925
The chip has two independent fault counters. Three
consecutive fault events on either outputs 1 or 3, or three
1.75V>
1.20V>
V CORE
1.2V VTT
consecutive fault events on output 2 will set the latch. Figure
7 details an example of such a situation where the overload
is removed before the counter increments to three and
latches the chip off. Time T0 marks the application of the
current overload. At time T1 a second fault is recorded, but
the overload is removed at time T2. Second restart attempt
at time T3 is successful, bringing the output in regulation and
1.50V>
1.80V>
1.5V AGP
1.8V MCH
resetting the fault counter.
FAULT DURATION
100 μ s/DIV.
+5V IN
FIGURE 5. ISL6523EVAL1 OUTPUT TRANSIENT RESPONSE
SS24 (TP7)
Output Short-Circuit Protection
In response to an overcurrent event on the switcher’s output, or
an undervoltage event on any of the linear outputs, the entire
chip is shut down. Figure 6 exemplifies such a scenario on
VOUT1 of the ISL6524EVAL1. At time T0, an overload is
applied to the core regulator output. Output current on this
output increases, ultimately tripping the overcurrent (OC)
GND>
V OUT1
5ms/DIV.
I OUT1
protection. The fault counter is incremented and SS24
capacitor is discharged, timing a restart attempt. The restart
T0
T1
T2
T3
takes place as the SS24 ramps up, and as the output voltage
builds up, a second OC event is triggered at T1. The fault
counter is incremented and the process repeats at time T2. At
time T3 the fault counter reaches a count of three and the chip
latches off. SS24 discharges down to about 1V, remaining at
this level until bias voltage is removed.
FAULT DURATION
+5V IN
SS24 (TP7)
V OUT1
I OUT1
GND>
10ms/DIV.
FIGURE 6B. ISL6524EVAL1 VOUT1 OVERCURRENT
PROTECTION RESPONSE
ISL6524EVAL1 Switching Regulator Efficiency
Figure 7 highlights the evaluation board’s conversion
efficiency with only the switching section loaded (V CORE ).
The measurement was performed at room temperature with
the linear outputs open and 100 LFM of air flow.
90
88
86
84
82
80
78
76
74
T0
T1
T2 T3
72
0
2
4
6
8 10 12 14
16
18
20
FIGURE 6A. ISL6524EVAL1 VOUT1 OVERCURRENT
OUTPUT CURRENT (A)
PROTECTION RESPONSE
FIGURE 7. ISL6524EVAL1 SWITCHING REGULATOR
MEASURED EFFICIENCY (ALL LINEAR
OUTPUTS UNLOADED)
4
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