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| 型号： | ISL6528CBZ-T |
| 厂商： | Intersil |
| 文件页数： | 10/13页 |
| 文件大小： | 361K |
| 描述： | IC REG DL BCK/LINEAR SYNC 8-SOIC |
| 标准包装： | 1 |
| 拓扑： | 降压（降压）同步（1），线性（LDO）（1） |
| 功能： | 任何功能 |
| 输出数： | 2 |
| 频率 - 开关： | 600kHz |
| 电压/电流 - 输出 1： | 控制器 |
| 电压/电流 - 输出 2： | 控制器 |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 无 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | * |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | * |
| 包装： | 标准包装 |
| 产品目录页面： | 1243 (CN2011-ZH PDF) |
| 其它名称： | ISL6528CBZ-TDKR |
10
FN9038.4
March 9, 2006
inductance value will slow the converter response time to a
load transient.
One of the parameters limiting the converters response to a
load transient is the time required to slew the inductor
current. Given a sufficiently fast control loop design, the
ISL6528 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
interval required to slew the inductor current from an initial
current value to the final current level. During this interval the
difference between the inductor current and the load current
must be supplied by the output capacitor(s). Minimizing the
response time can minimize the output capacitance
required.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
where I
TRAN
is the transient load current step, t
RISE
is the
response time to the application of load, and t
FALL
is the
response time to the removal of load.
With a +3.3V input source, the worst case response time can
be either at the application or removal of load and dependent
upon the output voltage setting. Be sure to check both of
these equations at the minimum and maximum output levels
for the worst case response time.
Input Capacitor Selection
The important parameters for the bulk input capacitors are
the voltage rating and the RMS current rating. For reliable
operation, select bulk input capacitors with voltage and
current ratings above the maximum input voltage and largest
RMS current required by the circuit. The capacitor voltage
rating should be at least 1.25 times greater than the
maximum input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 of the summation of the DC load current.
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitance
for the high frequency decoupling and bulk capacitors to
supply the RMS current. Small ceramic capacitors can be
placed very close to the upper MOSFET to suppress the
voltage induced in the parasitic circuit impedances. Connect
them directly to ground with a via placed very close to the
ceramic capacitor footprint.
For a through-hole design, several aluminum electrolytic
capacitors may be needed. For surface mount designs,
tantalum or special polymer capacitors can be used, but
caution must be exercised with regard to the capacitor surge
current rating. These capacitors must be capable of handling
the surge-current at power-up.
Transistor Selection/Considerations
The ISL6528 requires two external transistors. One N-
channel MOSFET is used as the upper switch in a standard
buck topology PWM converter. The linear controller drives
an NPN bipolar transistor as a pass element. The transistors
should be selected based upon r
DS(ON)
, current gain,
saturation voltages, gate/base supply requirements, and
thermal management considerations.
UPPER MOSFET SWITCH SELECTION
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components; conduction loss and switching loss. The
conduction losses account for a large portion of the power
dissipation of the MOSFET. Switching losses also contribute
to the overall MOSFET power loss.
where I
o
is the maximum load current, D is the duty cycle of
the converter (defined as V
O
/V
IN
), t
SW
is the switching
interval, and F
SW
is the PWM switching frequency.
These equations assume linear voltage-current transitions
and are approximations. The gate-charge losses are
dissipated by the ISL6528 and do not heat the MOSFET.
However, large gate-charge increases the switching interval,
t
SW
, which increases the upper MOSFET switching losses.
Ensure that the MOSFET is within its maximum junction
temperature at high ambient temperature by calculating the
temperature rise according to package thermal-resistance
specifications. A separate heatsink may be necessary
depending upon MOSFET power, package type, ambient
temperature, air flow, and load current requirements.
Given the reduced available gate bias voltage (5V) a logic-
level transistor is recommended for the upper switch. Close
attention to layout guidelines should be exercised with
devices exhibiting very low V
GS(on)
characteristics, as the
low gate threshold could lead to some shoot-through despite
counteracting circuitry present aboard the ISL6528.
NPN PASS TRANSISTOR SELECTION
A bipolar NPN transistor must be used with the linear
controller. Insure the current gain at the given operating V
CE
is sufficiently large to provide the desired maximum output
t
RISE
L
O
I
TRAN
?/DIV>
V
IN
V
OUT
--------------------------------
=
t
FALL
L
O
I
TRAN
?/DIV>
V
OUT
-------------------------------
=
(EQ. 13)
(EQ. 14)
P
Conduction
I
o
2
r
DS on
( )
?/DIV>
D
?/DIV>
E
P
Switching
1
2
---I
o
V
IN
?nbsp t
SW
?nbsp F
SW
?/DIV>
E
(EQ. 15)
(EQ. 16)
ISL6528
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