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| 型号： | ISL6528CBZ-T |
| 厂商： | Intersil |
| 文件页数： | 5/13页 |
| 文件大小： | 361K |
| 描述： | IC REG DL BCK/LINEAR SYNC 8-SOIC |
| 标准包装： | 1 |
| 拓扑： | 降压（降压）同步（1），线性（LDO）（1） |
| 功能： | 任何功能 |
| 输出数： | 2 |
| 频率 - 开关： | 600kHz |
| 电压/电流 - 输出 1： | 控制器 |
| 电压/电流 - 输出 2： | 控制器 |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 无 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | * |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | * |
| 包装： | 标准包装 |
| 产品目录页面： | 1243 (CN2011-ZH PDF) |
| 其它名称： | ISL6528CBZ-TDKR |
5
FN9038.4
March 9, 2006
Functional Pin Descriptions
GND (Pin 1)
Signal ground for the IC. All voltage levels are measured
with respect to this pin. Place via close to pin to minimize
impedance path to ground plane.
VCC (Pin 2)
Provide a well decoupled 5V bias supply for the IC to this
pin. The voltage at this pin is monitored for Power-On Reset
(POR) purposes.
DRIVE2 (Pin 3)
Connect this pin to the base terminal of an external bipolar
NPN transistor. This pin provides the base current drive for
the linear regulator pass transistor.
FB2 (Pin 4)
Connect the output of the linear regulator to this pin through
a properly sized resistor divider. The voltage at this pin is
regulated to 0.8V. This pin is also monitored for undervoltage
events.
Pulling and holding FB2 above 1.25V shuts down both
regulators. Releasing FB2 initiates soft-start on both
regulators.
FB (Pin 5) and COMP (Pin 6)
FB and COMP are the available external pins of the error
amplifier. The FB pin is the inverting input of the error amplifier
and the COMP pin is the error amplifier output. These pins are
used to compensate the voltage-mode control feedback loop of
the standard buck converter.
BOOT (Pin 7)
Connect a suitable capacitor (0.47礔 recommended) from
this pin to the source terminal of the upper MOSFET
(PHASE node). This bootstrap capacitor supplies the
UGATE driver the energy necessary to turn and hold the
upper MOSFET on. The absolute maximum voltage on
BOOT must be kept below 10V. This can be met with a 5V
VCC and 3.3V drain supply to the upper MOSFET.
UGATE (Pin 8)
Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the MOSFET.
Description
Operation Overview
The ISL6528 monitors and precisely controls two output
voltage levels. Refer to the Block Diagram, Simplified
Power System Diagram, and Typical Application Schematic
on pp. 23. The controller is intended for use in graphics
card or embedded processor applications with 3.3V and 5V
bias input available. The IC integrates both a standard buck
PWM controller and a linear controller. The PWM controller
is designed to regulate the high current GPU voltage
(V
OUT1
). The PWM controller drives a single N-Channel
MOSFET (Q1) in a standard buck converter configuration
and regulates the output voltage to a level programmed by
a resistor divider. The linear controller is designed to
regulate the lower current local memory voltage (V
OUT2
)
through an external NPN pass transistor.
Initialization
The ISL6528 automatically initializes upon application of
input power. Special sequencing of the input supplies is not
necessary. The POR function continually monitors the input
bias supply voltage at the VCC pin. The POR function
initiates soft-start operation after the 5V bias supply voltage
exceeds its POR threshold.
Soft-Start
The POR function initiates the digital soft-start sequence.
Both the linear regulator error amplifier and PWM error
amplifier reference inputs are forced to track a voltage level
proportional to the soft-start voltage. As the soft-start voltage
slews up, the PWM comparator regulates the output relative
to the tracked soft-start voltage slowly charging the output
capacitor(s). Simultaneously, the linear output follows the
smooth ramp of the soft-start function into normal regulation.
Figure 1 shows the soft-start sequence for a typical
application. At T0, the +5V VCC bias voltage starts to ramp
followed by the 3.3V input supply. Once the voltage on VCC
crosses the 4.4V POR threshold at time T1, both outputs
begin their soft-start sequence. The triangle waveform from
the PWM oscillator is compared to the rising error amplifier
output voltage. As the error amplifier voltage increases, the
pulse-width on the UGATE pin increases to reach its steady-
state duty cycle at time T2. The error amplifier reference of the
linear controller also rises relative to the soft-start reference.
The resulting soft ramp on DRIVE2 brings V
OUT2
within
regulation limits by time T2.
Undervoltage Protection
The FB and FB2 pins are monitored during converter
operation by two separate undervoltage (UV) comparators. If
the FB voltage drops below 52.5% of the reference voltage
(0.42V), a fault signal is generated. The internal fault logic
GND
VCC
DRIVE2
FB2
UGATE
FB
COMP
BOOT
8
7
6
5
1
2
3
4
ISL6528
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