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| 型号： | ISL6528CBZ-T |
| 厂商： | Intersil |
| 文件页数： | 7/13页 |
| 文件大小： | 361K |
| 描述： | IC REG DL BCK/LINEAR SYNC 8-SOIC |
| 标准包装： | 1 |
| 拓扑： | 降压（降压）同步（1），线性（LDO）（1） |
| 功能： | 任何功能 |
| 输出数： | 2 |
| 频率 - 开关： | 600kHz |
| 电压/电流 - 输出 1： | 控制器 |
| 电压/电流 - 输出 2： | 控制器 |
| 带 LED 驱动器： | 无 |
| 带监控器： | 无 |
| 带序列发生器： | 无 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | * |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | * |
| 包装： | 标准包装 |
| 产品目录页面： | 1243 (CN2011-ZH PDF) |
| 其它名称： | ISL6528CBZ-TDKR |
7
FN9038.4
March 9, 2006
The linear regulator output voltage is also set by means of
an external resistor divider as shown in Figure 4. The two
resistors used to set the output voltage should not exceed a
parallel equivalent value, referred to as R
FB
, of 5k&. This
restriction is due to the manner of implementation of the soft-
start function. The following relationship must be met:
To ensure the parallel combination of the feedback resistors
meets this criteria, choose a target value for R
FB
of less than
5k& and then apply the following equations:
where V
OUT2
is the desired linear regulator output voltage
and V
REF
is the internal reference voltage, 0.8V. For an
output voltage of 0.8V, simply populate R5 with a value less
than 5k& and do not populate R6.
Converter Shutdown
Pulling and holding the FB2 pin above a typical threshold of
1.28V will shutdown both regulators. Upon release of the
FB2 pin, the regulators enter into a soft-start cycle which
brings both outputs back into regulation.
PWM Controller Feedback Compensation
A simplified representation of the voltage-mode control loop
used for output regulation by the standard buck converter is
shown in Figure 5. The output voltage, V
OUT
, is fed back to
the negative input of the error amplifier which is regulated to
the reference voltage level, V
REF
. The error amplifier output,
V
E/A
, is compared with the triangle wave produced by the
oscillator, V
OSC
, to provide a pulse-width modulated (PWM)
signal from the PWM comparator. This signal is then used to
switch the MOSFET and produce a PWM waveform with an
amplitude of V
IN
at the PHASE node. The square-wave
PHASE voltage is then smoothed by the output filter, L
OUT
and C
OUT
, to produce a DC voltage level.
The modulator transfer function is defined as V
OUT
/V
E/A
.
The internal PWM comparator and driver circuits equate to a
DC gain block dominated by the supply voltage, V
IN
, divided
by the peak-to-peak magnitude of the triangle wave, V
OSC
.
The output filter components, L
OUT
and C
OUT
, shape the
overall modulator small-signal transfer function by
contributing a double pole break frequency at F
LC
and a
zero at F
ESR
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
and the impedance networks Z
IN
and Z
FB
. They provide the
link between the modulator transfer function and a
controllable closed loop transfer function of V
OUT
/V
REF
. The
goal of component selection for the compensation network is
to provide a loop gain with high 0dB crossing frequency
(f
0dB
) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f
0dB
and 180
degrees.
DRIVE2
FB2
C
OUT2
Q2
ISL6528
V
OUT2
+3.3V
IN
R5
R6
FIGURE 4. OUTPUT VOLTAGE SELECTION OF THE LINEAR
+
V
OUT2
0.8 1
R5
R6
--------
+
?nbsp ?/DIV>
?nbsp ?/DIV>
?/DIV>
=
R
FB
R5 R6
?/DIV>
R5 R6
+
---------------------- 5k&
<
=
(EQ. 2)
R5
V
OUT2
V
REF
-------------------
R
FB
?/DIV>
=
(EQ. 3)
R6
R5 V
REF
?/DIV>
V
OUT2
V
REF
----------------------------------------
=
(EQ. 4)
F
LC
1
2?nbsp L
O
C
O
?/DIV>
?/DIV>
----------------------------------------
=
F
ESR
1
2?ESR C
O
?/DIV>
?/DIV>
-----------------------------------------
=
(EQ. 5)
(EQ. 6)
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
V
REF
L
OUT
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
+
-
0.8V
R1
R3
R2
C3
C2
C1
COMP
V
OUT
FB
Z
FB
ISL6528
Z
IN
COMP
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
+
Z
FB
Z
IN
OSC
ISL6528
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