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参数资料
| 型号： | ISL6532AIRZ-T |
| 厂商： | Intersil |
| 文件页数： | 10/17页 |
| 文件大小： | 0K |
| 描述： | IC REG/CTRLR ACPI DUAL DDR 28QFN |
| 标准包装： | 4,000 |
| 应用： | 存储器，DDR/DDR2 稳压器 |
| 电流 - 电源： | 5.25mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN（6x6） |
| 包装： | 带卷 (TR) |
ISL6532A
S3
should be noted that the soft-start profile of the V TT LDO
output will vary according to the value of the capacitor on the
VREF_IN pin.
S5
12VATX 2V/DIV
S3
5VSBY
1V/DIV
V DDQ
500mV/DIV
S5
12VATX 2V/DIV
V AGP
500mV/DIV
V TT
500mV/DIV
V AGP
500mV/DIV
V DDQ
500mV/DIV
V TT_FLOAT
PGOOD
5V/DIV
V TT
500mV/DIV
2 048 CLOC K
2 048 CLOCK
CYCLES
CYCLES
PGOOD
12V POR
SOFT-START
INITIATES
SOFT-START ENDS
PGOOD COMPARATOR
5V/DIV
ENABLED
FIGURE 1. TYPICAL COLD START
and the V DDQ switching regulator will be disabled. NCH is
pulled low to disable the backfeed blocking MOSFET.
PGOOD will also transition LOW. When V TT is disabled, the
internal reference for the V TT regulator is internally shorted
to the V TT rail. This allows the V TT rail to float. When
floating, the voltage on the V TT rail will depend on the
leakage characteristics of the memory and MCH I/O pins. It
is important to note that the V TT rail may not bleed down to 0V.
The V DDQ rail will be supported in the S3 state through the
standby V DDQ LDO. When S3 transitions LOW, the Standby
regulator is immediately enabled. The switching regulator is
disabled synchronous to the switching waveform. The shut
off time will range between 4μs and 8μs. The standby LDO is
capable of supporting up to 650mA of load with P5VSBY tied
to the 5V Standby Rail. The standby LDO may receive input
from either the 3.3V Standby rail or the 5V Standby rail
through the P5VSBY pin. It is recommended that the 5V
Standby rail be used as the current delivery capability of the
LDO is greater.
SLEEP TO ACTIVE (S3 TO S0 TRANSITION)
When SLP_S3 transitions from LOW to HIGH with SLP_S5
held HIGH and after the 12V rail exceeds POR, the
ISL6532A will enable the V DDQ switching regulator, disable
the V DDQ standby regulator, enable the V TT LDO and force
the NCH pin to a high impedance state turning on the
blocking MOSFET. The AGP LDO goes through a 2048
clock cycle soft-start. The internal short between the V TT
reference and the V TT rail is released. Upon release of the
short, the capacitor on VREF_IN is then charged up through
the internal resistor divider network. The V TT output will
follow this capacitor charge up, and acting as the S3 to S0
transition soft-start for the V TT rail. The PGOOD comparator
is enabled only after 2048 clock cycles, or typically 8.2ms,
have passed following the S3 transition to a HIGH state.
Figure 2 illustrates a typical state transition from S3 to S0. It
10
2048 CLOCK
CYCLES
12V POR PGOOD COMPARATOR
ENABLED
FIGURE 2. TYPICAL S3 to S0 STATE TRANSITION
ACTIVE TO SHUTDOWN (S0 TO S5 TRANSITION)
When the system transitions from active (S0) state to
shutdown (S4/S5) state, the ISL6532A IC disables all
regulators and forces the PGOOD pin and the NCH pin
LOW.
V DDQ Overcurrent Protection (S0 State)
The overcurrent function protects the switching converter
from a shorted output by using the upper MOSFET ON-
resistance, r DS(ON) , to monitor the current. This method
enhances the converter’s efficiency and reduces cost by
eliminating a current sensing resistor.
The overcurrent function cycles the soft-start function in a
hiccup mode to provide fault protection. A resistor (R OCSET )
programs the overcurrent trip level (see Typical Application
Diagrams on page 4 and page 5). An internal 20 μ A (typical)
current sink develops a voltage across R OCSET that is
referenced to the converter input voltage. When the voltage
across the upper MOSFET (also referenced to the converter
input voltage) exceeds the voltage across R OCSET , the
over-current function initiates a soft-start sequence. The
initiation of soft-start will affect all regulators. The V TT
regulator is directly affected as it receives it’s reference from
V DDQ . The AGP LDO will also be soft-started, and as such,
the AGP LDO voltage will be disabled while the V DDQ
regulator is disabled.
Figure 3 illustrates the protection feature responding to an
overcurrent event. At time T0, an overcurrent condition is
sensed across the upper MOSFET. As a result, the regulator
is quickly shutdown and the internal soft-start function
begins producing soft-start ramps. The delay interval seen
by the output is equivalent to three soft-start cycles. The
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