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参数资料
| 型号： | ISL6532CCR |
| 厂商： | Intersil |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | IC REG/CTRLR ACPI DUAL DDR 28QFN |
| 标准包装： | 50 |
| 应用： | 存储器，DDR/DDR2 稳压器 |
| 电流 - 电源： | 5.25mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN（6x6） |
| 包装： | 管件 |
ISL6532C
The PWM wave is smoothed by the output filter (L O and C O ).
4. Place 1 ST Pole at the ESR Zero.
OSC
DRIVER
V IN
5. Place 2 ND Pole at Half the Switching Frequency.
? V OSC
PWM
COMPARATOR
-
+
DRIVER
L O
PHASE
C O
V DDQ
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
F Z1 = ------------------------------------
F P1 = ---------------------------------------------------------
2 π x R 2 x ? ---------------------- ?
V E/A
Z FB
ESR
(PARASITIC)
1
2 π x R 2 x C 2
1
? C 1 x C 2 ?
? C 1 + C 2 ?
F Z2 = -------------------------------------------------------
F P2 = ------------------------------------
-
+
ERROR
Z IN
REFERENCE
1
2 π x ( R 1 + R 3 ) x C 3
1
2 π x R 3 x C 3
AMP
DETAILED COMPENSATION COMPONENTS
Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high
C 1
C 2
COMP
R 2
Z FB
C 3
Z IN
R 1
R 3
V DDQ
gain peak due to the high Q factor of the output filter and is
not shown in Figure 6. Using the above guidelines should
give a Compensation Gain similar to the curve plotted. The
open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at F P2 with the
capabilities of the error amplifier. The Closed Loop Gain is
-
+
FB
R 4
constructed on the graph of Figure 6 by adding the
Modulator Gain (in dB) to the Compensation Gain (in dB).
This is equivalent to multiplying the modulator transfer
V DDQ = 0.8 × ? 1 + ------ 1 - ?
ISL6532C
REFERENCE
? R ?
? R 4 ?
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
The modulator transfer function is the small-signal transfer
function of V OUT /V E/A . This function is dominated by a DC
function to the compensation transfer function and plotting
the gain.
The compensation gain uses external impedance networks
Z FB and Z IN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Gain and the output filter (L O and C O ), with a double pole
break frequency at F LC and a zero at F ESR . The DC Gain of
the modulator is simply the input voltage (V IN ) divided by the
peak-to-peak oscillator voltage ? V OSC .
100
80
60
F Z1 F Z2
F P1
F P2
OPEN LOOP
ERROR AMP GAIN
Modulator Break Frequency Equations
40
20LOG
F LC = -------------------------------------------
LO x CO
F ESR = --------------------------------------------
2 π x
1
1
2 π x ESR x C O
20
0
(R 2 /R 1 )
20LOG
(V IN / ? V OSC )
The compensation network consists of the error amplifier
-20
MODULATOR
GAIN
COMPENSATION
GAIN
(internal to the ISL6532C) and the impedance networks Z IN
and Z FB . The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
-40
-60
10
100
1K
F LC
10K
F ESR
100K
1M
CLOSED LOOP
GAIN
10M
frequency (f 0dB ) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f 0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R 1 , R 2 ,
R 3 , C 1 , C 2 , and C 3 ) in Figure 5. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R 2 /R 1 ) for desired converter bandwidth.
2. Place 1 ST Zero Below Filter’s Double Pole (~75% F LC ).
3. Place 2 ND Zero at Filter’s Double Pole.
12
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Feedback Compensation - AGP LDO Controller
Figure 7 shows the AGP LDO power and control stage. This
LDO, which uses a MOSFET as the linear pass element,
requires feedback compensation to insure stability of the
system. The LDO requires compensation because of the
output impedance of the error amplifier.
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| ISL6532CCRZ | 功能描述:IC REG/CTRLR ACPI DUAL DDR 28QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 电源管理 - 专用 系列:- 应用说明:Ultrasound Imaging Systems Application Note 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:37 系列:- 应用:医疗用超声波成像，声纳 电流 - 电源:- 电源电压:2.37 V ~ 6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:56-WFQFN 裸露焊盘 供应商设备封装:56-TQFN-EP（8x8） 包装:管件 |
| ISL6532CCRZ-T | 功能描述:IC REG/CTRLR ACPI DUAL DDR 28QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 电源管理 - 专用 系列:- 应用说明:Ultrasound Imaging Systems Application Note 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:37 系列:- 应用:医疗用超声波成像，声纳 电流 - 电源:- 电源电压:2.37 V ~ 6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:56-WFQFN 裸露焊盘 供应商设备封装:56-TQFN-EP（8x8） 包装:管件 |
| ISL6532CR | 功能描述:IC REG/CTRLR ACPI DUAL DDR 20QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 电源管理 - 专用 系列:- 应用说明:Ultrasound Imaging Systems Application Note 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:37 系列:- 应用:医疗用超声波成像，声纳 电流 - 电源:- 电源电压:2.37 V ~ 6 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:56-WFQFN 裸露焊盘 供应商设备封装:56-TQFN-EP（8x8） 包装:管件 |
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