参数资料
| 型号： | ISL65426HRZ |
| 厂商： | Intersil |
| 文件页数： | 17/22页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 6A DL 50QFN |
| 产品培训模块： | Dual Synchronous Integrated FET Buck Regulator Solutions for Industrial Control Applications |
| 标准包装： | 30 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 1 V ~ 4 V |
| 输入电压： | 3 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1MHz |
| 电流 - 输出： | 6A |
| 同步整流器： | 是 |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 50-VFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 50-QFN（5x10） |
| 产品目录页面： | 1248 (CN2011-ZH PDF) |
ISL65426
enable level is defined in Equation 2. R 1 is the resistor EN to
VCC2 and R 2 is the resistor from EN to GND.
decoded valid configuration. The master power block of
output Channel 2 (Power Block 5) pulses, and again, the LX
V ENABLE = R 1 ? ------------ + 10 μ A + 0.6V
0.6V
R 2
(EQ. 2)
pins of the other non-master blocks are monitored. The
common LX connections are checked versus the decoded
valid configuration. Each floating power block has a pull-down
Once the voltage at the EN pin reaches the enable
threshold, the 10μA current sink turns off.
With the part enabled and the current sink off, the disable
level is set by the resistor divider. The disable level is
defined in Equation 3.
active only during the configuration check to remove noise
related false positive detections.
A successful configuration check initiates a soft-start interval
100μs after completion. Failing the configuration check, the
controller will attempt a configuration check again 100μs
V DISABLE = 0.6V ? ---------------------
R 1 + R 2
R 2
(EQ. 3)
after completing the first check cycle. The controller repeats
the configuration check cycle every 100μs until a valid
configuration is detected or the controller is powered down.
The difference between the enable and disable levels
provides the user with configurable hysteresis to prevent
premature tripping.
To enable the controller, the system enable must be high,
and one or both of the channel enables must be high. The
POR circuitry must be satisfied for both VCC and PVINx
inputs. Once these conditions are met, the controller
immediately initiates a power block configuration check.
Once successful, the configuration check is not implemented
again until VCC falls below the POR falling threshold.
Re-enabling the controller after a successful configuration
check will immediately initiate a soft-start interval.
Soft-start Interval
Once the controller is enabled and power block configuration
is successful, the digital soft-start function clamps the error
amplifier reference. The digital soft-start circuitry ramps the
ISL65426
EXTERNAL CONDITIONS
+VCC1
VCC
output voltage by stepping the reference up gradually over a
fixed interval of 4ms. The controlled ramp of the output
voltage reduces the in-rush current during startup.
Power-good Signal
Each power-good pin (PG1, PG2) is an open-drain logic
output that indicates when the converter output voltage is
SYSTEM ENABLE
COMPARATOR
+
EN
+VCC2
R1
within regulation limits. The power-good pins pull low during
shutdown and remain low when the controller is enabled.
After a successful converter channel soft-start, the
power-good pin signal associated with that channel releases
POR
LOGIC
-
0.6V
10μA
R2
and the power-good pin voltage rises with an external pull-up
resistor. The power-good signal transitions low immediately
upon the removal of individual channel or system enable.
The power-good circuitry monitors both output voltage FB
pins and compares them to the rising and falling limits shown
in the “Electrical Specifications” table. If either channel’s
feedback voltage exceeds the typical rising limit of 115% of
FIGURE 37. SYSTEM ENABLE INPUT
Power Block Configuration Check
After VCC exceeds its POR rising threshold, the controller
decodes ISET1 and ISET2 states into one of four valid
power block configurations (see Table 1). These pins are not
checked again unless VCC falls below the POR falling
threshold. The valid configuration is saved for comparison
with the LX slave connectivity result, which is determined
during the configuration check.
Once the POR and enable circuitry is satisfied, the controller
initiates a configuration check. The master power block of
output Channel 1 (Power Block 2) pulses high for 100ns. The
configuration check circuitry detects which power blocks
share a common LX connection and compares this to the
17
the reference voltage, the power-good pin pulls low. The
power-good pin continues to pull low until the feedback
voltage recovers down by a typical of 110% of the reference
voltage. If either channel’s feedback voltage drops below a
typical of 85% of the reference voltage, the power-good pin
related to the offending channel(s) pulls low. The power-good
pin continues to pull low until the feedback voltage rises to
within 90% of the reference voltage. The power-good pin then
releases and signals the return of the output voltage within the
power-good window.
Fault Monitoring and Protection
The ISL65426 actively monitors output voltage and current
to detect fault conditions. Fault monitors trigger protective
measures to prevent damage to the controller and external
FN6340.3
March 25, 2008
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| ISL65426HRZS2698 | 制造商:Intersil Corporation 功能描述:LEAD-FREE W/ANNEAL, DUAL BUCK REGULATOR. -10 TO +100 TEMP. - Rail/Tube 制造商:Intersil 功能描述:W/ANNEAL DL BUCKG -10 TO +100 TEMP |
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| ISL65426HRZ-T | 功能描述:IC REG BUCK SYNC ADJ 6A DL 50QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:降压（降压） 输出类型:两者兼有 输出数:1 输出电压:5V，1 V ~ 10 V 输入电压:3.5 V ~ 28 V PWM 型:电流模式 频率 - 开关:220kHz ~ 1MHz 电流 - 输出:600mA 同步整流器:无 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:16-SSOP（0.154"，3.90mm 宽） 包装:带卷 (TR) 供应商设备封装:16-QSOP |
| ISL65426HRZ-TS2698 | 制造商:Intersil Corporation 功能描述:LEAD-FREE W/ANNEAL, DUAL BUCK REGULATOR. -10 TO +100 TEMP. - Tape and Reel 制造商:Intersil 功能描述:W/ANNEAL DL BUCKG -10 TO +100 TEMP |
| ISL65426HRZ-TS2715 | 制造商:Intersil Corporation 功能描述:S SPEC FOR TRACKING BROADCOM BUSINESS ONLY-SOLD THRU DISTI - Tape and Reel |
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