参数资料
| 型号： | ISL65426HRZ |
| 厂商： | Intersil |
| 文件页数： | 19/22页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 6A DL 50QFN |
| 产品培训模块： | Dual Synchronous Integrated FET Buck Regulator Solutions for Industrial Control Applications |
| 标准包装： | 30 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 1 V ~ 4 V |
| 输入电压： | 3 V ~ 5.5 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 1MHz |
| 电流 - 输出： | 6A |
| 同步整流器： | 是 |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 50-VFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 50-QFN（5x10） |
| 产品目录页面： | 1248 (CN2011-ZH PDF) |
ISL65426
Δ V ≈ ESL × ----- + [ ESR × Δ I ]
dt
L ≤ ------------------------- Δ V MAX – ( Δ I ? ESR )
L ≤ ------------------------- Δ V MAX – ( Δ I ? ESR ) ? V IN – V O ?
( Δ I ) 2
regulator response, the output voltage initially deviates by an
amount shown in Equation 4.
di
(EQ. 4)
The filter capacitors selected must have sufficiently low ESL
2 ? C ? V O
( Δ I ) 2
( 1.25 ) ? C
? ?
(EQ. 8)
(EQ. 9)
C OUT = 0.5 × Number of LX channels used × 150 μ F × ----------------
and ESR so that the total output voltage deviation Δ V is less
than the maximum allowable ripple.
The recommended load capacitance can be estimated using
Equation 5.
1.8V
V OUT
(EQ. 5)
The internal compensation scheme assumes low-ESR
output capacitors. It is recommended to only use specialty
polymer or ceramic capacitors with ESRs of 10m Ω or lower.
The other concern when selecting an output inductor is the
internally set current mode slope compensation. Designs
should not allow inductor ripple currents below 0.125 times
the maximum output current to prevent regulation issues.
It is recommended to use a 30% peak-to-peak ripple current
value to calculate out the inductance required for the
application. Accordingly, the inductance estimated using
Equation 10 below would fall between the minimum
inductance value calculated in Equation 7 and the maximum
values determined from Equations 8 and 9.
( V IN – V OUT ) × V OUT
I OUT
V IN × f s × -----------------------------
Care also needs to be taken to ensure that the dielectric of
the capacitor used will work reliably in the entire temperature
range of the application.
L @ ----------------------------------------------------------------
MAX
3
(EQ. 10)
Design Example:
Consider an output voltage of 1.2V, with LX1, LX2, LX3 and
LX4 connected. The output capacitance required would be:
Input Capacitor Selection
Input capacitors are responsible for sourcing the AC
component of the input current flowing into the switching
C OUT = 0.5 ? 4 ? 150 μ F ? ------------ = 450 μ F
1.8V
1.2V
(EQ. 6)
power devices. Their RMS current capacity must be
sufficient to handle the AC component of the current drawn
A 330μF specialty polymer capacitor in parallel with three
47μF X7R ceramic capacitors would be the recommended
choice of output filter.
by the switching power devices, which is related to duty
cycle. The maximum RMS current required by the regulator
is closely approximated by Equation 11.
----------------- × ? I
1 ? V IN – V OUT V OUT ? 2 ?
L × fs
V IN ? ?
?
OUTPUT INDUCTOR SELECTION
I
RMS MAX
=
V OUT ?
V IN ?
OUT MAX
2
+ ------ × ? ---------------------------------- × ----------------- ? ?
12
Once the output capacitors are selected, the maximum
allowable ripple voltage, V PPMAX , determines the lower limit
on the inductance. See Equation 7.
(EQ. 11)
The important parameters to consider when selecting an
input capacitor are the voltage rating and the RMS current
( V IN – V OUT ) V OUT
f s × V IN × V PP
L ≥ ESR × -----------------------------------------------------
MAX
(EQ. 7)
rating. For reliable operation, select capacitors with voltage
ratings above the maximum input voltage. The rated voltage
rating should be at least 1.25 times greater than the
Since the output capacitors are supplying a decreasing
portion of the load current while the regulator recovers from
the transient, the capacitor voltage becomes slightly
depleted. The output inductors must be capable of assuming
the entire load current before the output voltage decreases
more than Δ V MAX . This places an upper limit on inductance.
Equation 8 gives the upper limit on output inductance for the
cases when the trailing edge of the current transient causes
the greater output voltage deviation than the leading edge.
Equation 9 addresses the leading edge. Normally, the
trailing edge dictates the inductance selection because duty
cycles are usually less than 50%. Nevertheless, both
inequalities should be evaluated, and inductance should be
governed based on the lower of the two results. In each
equation, L is the output inductance and C is the total output
capacitance.
19
maximum input voltage while using aluminum electrolytic
capacitors, and about 2 times the maximum input voltage to
account for capacitance derating in case of ceramic
capacitors. The capacitor RMS current rating should be
higher than the largest RMS current required by the circuit.
The ISL65426 needs a minimum effective input capacitance
of 70μF with low ESR for stable operation.
Layout Considerations
Careful printed circuit board (PCB) layout is critical in high
frequency switching converter design. Current transitions
from one device to another at this frequency induce voltage
spikes across the interconnecting impedances and parasitic
elements. These spikes degrade efficiency, lead to device
overvoltage stress, radiate noise into sensitive nodes, and
increase thermal stress on critical components. Careful
component placement and PCB layout minimizes the
voltage spikes in the converter.
FN6340.3
March 25, 2008
相关PDF资料 |
PDF描述 |
|---|---|
| ISL6545IBZ-T | IC REG CTRLR BUCK PWM VM 8-SOIC |
| ISL6548ACRZA-T | IC REG/CTLR ACPI DUAL DDR 28QFN |
| ISL6548CRZA | IC REG/CTRLR ACPI DUAL DDR 28QFN |
| ISL6551IR-T | IC REG CTRLR FLYBACK PWM 28-QFN |
| ISL6552CR-T | IC REG CTRLR BUCK PWM 20-QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL65426HRZS2698 | 制造商:Intersil Corporation 功能描述:LEAD-FREE W/ANNEAL, DUAL BUCK REGULATOR. -10 TO +100 TEMP. - Rail/Tube 制造商:Intersil 功能描述:W/ANNEAL DL BUCKG -10 TO +100 TEMP |
| ISL65426HRZS2715 | 制造商:Intersil Corporation 功能描述:S SPEC FOR TRACKING BROADCOM BUSINESS ONLY-SOLD THRU DISTI - Rail/Tube |
| ISL65426HRZ-T | 功能描述:IC REG BUCK SYNC ADJ 6A DL 50QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 类型:降压（降压） 输出类型:两者兼有 输出数:1 输出电压:5V，1 V ~ 10 V 输入电压:3.5 V ~ 28 V PWM 型:电流模式 频率 - 开关:220kHz ~ 1MHz 电流 - 输出:600mA 同步整流器:无 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:16-SSOP（0.154"，3.90mm 宽） 包装:带卷 (TR) 供应商设备封装:16-QSOP |
| ISL65426HRZ-TS2698 | 制造商:Intersil Corporation 功能描述:LEAD-FREE W/ANNEAL, DUAL BUCK REGULATOR. -10 TO +100 TEMP. - Tape and Reel 制造商:Intersil 功能描述:W/ANNEAL DL BUCKG -10 TO +100 TEMP |
| ISL65426HRZ-TS2715 | 制造商:Intersil Corporation 功能描述:S SPEC FOR TRACKING BROADCOM BUSINESS ONLY-SOLD THRU DISTI - Tape and Reel |
发布紧急采购，3分钟左右您将得到回复。