参数资料
| 型号： | ISL6551IR-T |
| 厂商： | Intersil |
| 文件页数： | 12/26页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR FLYBACK PWM 28-QFN |
| 标准包装： | 4,000 |
| PWM 型： | 电流模式 |
| 输出数： | 6 |
| 频率 - 最大： | 1MHz |
| 占空比： | 50% |
| 电源电压： | 10.8 V ~ 13.2 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 28-VQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6551
- Per Equation 3, the clamping voltage is a function of the
charge current Iss. For a more predictable clamping
voltage, the CSS pin can be connected to a reference-
based clamp circuit as shown in Figure 5. To make the
Vclamp less dependent on the soft-start current (Iss),
the currents flowing through R1 and R2 should be
in a short-circuit condition. The limit can be set with a
resistor divider from the ISENSE pin. The resistor divider
relationship is defined in Equation 7.
- In general, the trip point is a little smaller than the BGREF
due to the noise and/or ripple at the BGREF.
scaled much greater than Iss. The relationship of this
circuit can be found in Equation 4.
V REF
R UP
R DOWN
ISENSE
PKILIM
R1
CSS
FIGURE 6. PEAK CURRENT LIMIT SET CIRCUIT
R2
-------------------------------------- = -----------------------------------------
Rdown BGREF
Rdown + Rup ISENSE ( max )
(EQ. 7)
FIGURE 5. REFERENCE-BASED CLAMP CIRCUIT
? Latching Shutdown (LATSD)
- A high TTL level on LATSD latches the IC off. The IC goes
Vclamp ≈ Iss ? ---------------------- + Vref ? ----------------------
R1 × R2 R2
R1 + R2 R1 + R2
(EQ. 4)
into a low power mode and is reset only after the power at
the VDD pin is removed completely. The ON/OFF cannot
reset the latch.
- The soft-start rise time (T ss ) can be calculated with
Equation 5. The rise time (T rise ) of the output voltage is
approximated with Equation 6.
- This pin can be used to latch the power supply off on
output overvoltage or other undesired conditions.
? ON/OFF (ON/OFF)
Vclamp × Css
Iss
T ss = ---------------------------------------
(s)
(EQ. 5)
- A high standard TTL input (safe also for VDD level) signals
the controller to turn on. A low TTL input turns off the
controller and terminates all drive signals including the
SYNC outputs. The soft-start is reset.
T rise = --------------------------------
EANI × Css
Iss
(s)
(EQ. 6)
- This pin is a non-latching input and can accept an enable
command when monitoring the input voltage and the
thermal condition of a converter.
? Drivers (Upper1, Upper2, Lower1, Lower2)
- The two upper drivers are driven at a fixed 50% duty
cycle and the two lower drivers are PWM-controlled on
the trailing edge while the leading edge employs resonant
delay. They are biased by VDDP1 and VDDP2,
? Resonant Delay (R_RESDLY)
- A resistor tied between R_RESDLY and VSS determines
the delay that is required to turn on a lower FET after its
corresponding upper FET is turned off. This is the resonant
delay, which can be estimated with Equation 8.
respectively.
- Each driver is capable of driving capacitive loads up to CL
t RESDLY = 4.01 x R_RESDLY/k ? + 13 (ns)
(EQ. 8)
at 1MHz clock frequency and higher loads at lower
frequencies on a layout with high effective thermal
conductivity.
- The UVLO holds all the drivers low until the VDD has
reached the turn-on threshold VDD ON .
- The upper drivers require assistance of external level-
shifting circuits such as Intersil’s HIP2100 or pulse
transformers to drive the upper power switches of a bridge
converter.
? Peak Current Limit (PKILIM)
- When the voltage at PKILIM exceeds the BGREF voltage,
the gate pulses are terminated and held low until the next
clock cycle. The peak current limit circuit has a high-speed
loop with propagation delay IpkDel. Peak current
shutdown initiates a soft-start sequence.
- The peak current shutdown threshold is usually set slightly
higher than the normal cycle-by-cycle PWM peak current
limit (Vclamp) and therefore will normally only be activated
12
- Figure 7 illustrates the relationship of the value of the
resistor (R_RESDLY) and the resonant delay (t RESDLY ).
The percentages in the figure are the tolerances at the two
end points of the curve.
FN9066.5
January 3, 2006
相关PDF资料 |
PDF描述 |
|---|---|
| ISL6552CR-T | IC REG CTRLR BUCK PWM 20-QFN |
| ISL6553CB-T | IC REG CTRLR BUCK PWM 16-SOIC |
| ISL6554CB-T | IC PWM CORE VOLTAGE REG 20-SOIC |
| ISL6556ACR-T | IC CTRLR MULTIPHASE VRM10 32-QFN |
| ISL6556BCR-T | IC CTRLR MULTIPHASE VRM10 32-QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6551IRZ | 功能描述:IC REG CTRLR FLYBACK PWM 28-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR) |
| ISL6552CB | 功能描述:IC REG CTRLR BUCK PWM 20-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR) |
| ISL6552CB-T | 功能描述:IC REG CTRLR BUCK PWM 20-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR) |
| ISL6552CBZ | 功能描述:IC REG CTRLR BUCK PWM 20-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6552CBZA | 功能描述:IC REG CTRLR BUCK PWM 20-SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
发布紧急采购，3分钟左右您将得到回复。