参数资料
| 型号： | ISL6556BCB-T |
| 厂商： | Intersil |
| 文件页数： | 11/24页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR MULTIPHASE VRM10 28SOIC |
| 标准包装： | 1,000 |
| 应用： | 控制器，Intel VR10X |
| 输入电压： | 3 V ~ 12 V |
| 输出数： | 4 |
| 输出电压： | 0.84 V ~ 1.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 带卷 (TR) |
ISL6556B
Figures 14, 16 and 16 in the section entitled Input Capacitor
Selection can be used to determine the input-capacitor RMS
current based on load current, duty cycle, and the number of
channels. They are provided as aids in determining the
switching cycle. The sampled current, I n , is used for channel-
current balance, load-line regulation, overcurrent protection,
and module current sharing. From Figure 3, the following
equation for I n is derived
I n = I L ---------------------- )
optimal input capacitor solution. Figure 17 shows the single
phase input-capacitor RMS current for comparison.
r DS ( ON
R ISEN
(EQ. 3)
PWM Operation
The timing of each converter leg is set by the number of
active channels. The default channel setting for the
ISL6556B is four. One switching cycle is defined as the time
between PWM1 pulse termination signals. The pulse
termination signal is the internally generated clock signal
that triggers the falling edge of PWM1. The cycle time of the
pulse termination signal is the inverse of the switching
frequency set by the resistor between the FS pin and
ground. Each cycle begins when the clock signal commands
where I L is the channel current.
If R DS(ON) sensing is not desired, an independent current-
sense resistor in series with the lower MOSFET source can
serve as a sense element. The circuitry shown in Figure 3
represents channel n of an N-channel converter. This
circuitry is repeated for each channel in the converter, but
may not be active depending upon the status of the PWM3
and PWM4 pins as described under PWM Operation
section.
I SEN = I ------------------------- ) -
L R
the channel-1 PWM output to go low. The PWM1 transition
signals the channel-1 MOSFET driver to turn off the
channel-1 upper MOSFET and turn on the channel-1
synchronous MOSFET. In the default channel configuration,
I n
r DS ( ON
ISEN
V IN
CHANNEL N
UPPER MOSFET
the PWM2 pulse terminates 1/4 of a cycle after PWM1. The
PWM3 output follows another 1/4 of a cycle after PWM2.
PWM4 terminates another 1/4 of a cycle after PWM3.
SAMPLE
&
HOLD
ISEN(n)
I L
If PWM3 is connected to VCC, two channel operation is
selected and the PWM2 pulse terminates 1/2 of a cycle later.
Connecting PWM4 to VCC selects three channel operation
and the pulse-termination times are spaced in 1/3 cycle
-
+
R ISEN
CHANNEL N
-
+
I L r DS ( ON )
increments.
LOWER MOSFET
Once a PWM signal transitions low, it is held low for a
ISL6556B INTERNAL CIRCUIT
EXTERNAL CIRCUIT
I 1 + I 2 + + I N
I AVG = ----------------------------------------
N
I AVG = ------------- ---------------------- )
R ISEN
minimum of 1/3 cycle. This forced off time is required to
ensure an accurate current sample. Current sensing is
described in the next section. After the forced off time
expires, the PWM output is enabled. The PWM output state
is driven by the position of the error amplifier output signal,
V COMP , minus the current correction signal relative to the
sawtooth ramp as illustrated in Figure 4. When the modified
V COMP voltage crosses the sawtooth ramp, the PWM output
transitions high. The MOSFET driver detects the change in
state of the PWM signal and turns off the synchronous
MOSFET and turns on the upper MOSFET. The PWM signal
will remain high until the pulse termination signal marks the
beginning of the next cycle by triggering the PWM signal low.
Current Sensing
During the forced off time following a PWM transition low, the
controller senses channel current by sampling the voltage
across the lower MOSFET r DS(ON) (see Figure 3). A ground-
referenced operational amplifier, internal to the ISL6556B, is
connected to the PHASE node through a resistor, R ISEN .
The voltage across R ISEN is equivalent to the voltage drop
across the r DS(ON) of the lower MOSFET while it is
conducting. The resulting current into the ISEN pin is
proportional to the channel current, I L . The ISEN current is
sampled and held after sufficient settling time every
11
FIGURE 3. INTERNAL AND EXTERNAL CURRENT-SENSING
CIRCUITRY
Channel-Current Balance
The sampled current, I n , from each active channel is used to
gauge both overall load current and the relative channel
current carried in each leg of the converter. The individual
sample currents are summed and divided by the number of
active channels. The resulting average current, I AVG ,
provides a measure of the total load current demand on the
converter and the appropriate level of channel current. Using
Figures 3 and 4, the average current is defined as
…
(EQ. 4)
I OUT r DS ( ON
N
where N is the number of active channels and I OUT is the
total load current.
The average current is subtracted from the individual
channel sample currents. The resulting error current, I ER , is
filtered to modify V COMP . The modified V COMP signal is
compared to a sawtooth ramp signal to produce a modified
FN9097.4
December 28, 2004
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6556BCBZ | 功能描述:电流型 PWM 控制器 VRM 10 0 MULTI-PHS CONTROLLER RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6556BCBZ | 制造商:Intersil Corporation 功能描述:Pulse Width Modulation (PWM) Controller |
| ISL6556BCBZ-T | 功能描述:电流型 PWM 控制器 VRM 10 0 MULTI-PHS CONTROLLER RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6556BCR | 功能描述:IC CTRLR MULTIPHASE VRM10 32-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,000 系列:- 应用:电源，ICERA E400，E450 输入电压:4.1 V ~ 5.5 V 输出数:10 输出电压:可编程 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:42-WFBGA，WLCSP 供应商设备封装:42-WLP 包装:带卷 (TR) |
| ISL6556BCRR5148 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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