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| 型号： | ISL6559CB |
| 厂商： | Intersil |
| 文件页数： | 8/21页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 28-SOIC |
| 标准包装： | 26 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 4MHz |
| 占空比： | 75% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 包装： | 管件 |
ISL6559
V IN
active channels. The resulting average current, I AVG ,
DS ( ON )
I n
I
r
R
SEN = I L --------------------------
ISEN
CHANNEL N
UPPER MOSFET
provides a measure of the total load current demand on the
converter and the appropriate level of channel current. Using
Figures 3 and 4, the average current is defined as
I AVG = ----------------------------------
SAMPLE
&
HOLD
ISEN(n)
I L
I 1 + I 2 + … I N
N
(EQ. 4)
I AVG = ------------- ---------------------- )
R ISEN
-
+
R ISEN
-
I L r DS ( ON )
I OUT r DS ( ON
N
+
CHANNEL N
LOWER MOSFET
where N is the number of active channels and I OUT is the
total load current.
ISL6559 INTERNAL CIRCUIT
EXTERNAL CIRCUIT
The average current is then subtracted from the individual
FIGURE 3. INTERNAL AND EXTERNAL CURRENT-SENSING
CIRCUITRY
across the R DS(ON) of the lower MOSFET while it is
conducting. The resulting current into the ISEN pin is
proportional to the channel current, I L . The ISEN current is
then sampled and held after sufficient settling time every
switching cycle. The sampled current, I n , is used for channel-
current balance, load-line regulation, overcurrent protection,
and module current sharing. From Figure 3, the following
equation for I n is derived:
channel sample currents. The resulting error current, I ER , is
then filtered before it adjusts V COMP . The modified V COMP
signal is compared to a sawtooth ramp signal and produces
a pulse width which corrects for any unbalance and drives
the error current toward zero. Figure 4 illustrates Intersil’s
patented current-balance method as implemented on
channel-1 of a multi-phase converter.
Two considerations designers face are MOSFET selection
and inductor design. Both are significantly improved when
channel currents track at any load level. The need for
I n = I L ---------------------- )
r DS ( ON
R ISEN
(EQ. 3)
complex drive schemes for multiple MOSFETs, exotic
magnetic materials, and expensive heat sinks is avoided.
Resulting in a cost-effective and easy to implement solution
where I L is the channel current.
If R DS(ON) sensing is not desired, an independent current-
sense resistor in series with the lower MOSFET source can
serve as a sense element. The circuitry shown in Figure 3
represents channel n of an N-channel converter. This
circuitry is repeated for each channel in the converter, but
may not be active depending upon the status of the PWM3
and PWM4 pins as described in the previous section.
Channel-Current Balance
The sampled current, I n , from each active channel is used to
gauge both overall load current and the relative channel
current carried in each leg of the converter. The individual
sample currents are summed and divided by the number of
relative to single-phase conversion. Channel-current balance
insures the thermal advantage of multi-phase conversion is
realized. Heat dissipation is spread over multiple channels
and a greater area than single phase approaches.
In some circumstances, it may be necessary to deliberately
design some channel-current unbalance into the system. In
a highly compact design, one or two channels may be able to
cool more effectively than the other(s) due to nearby air flow
or heat sinking components. The other channel(s) may have
more difficulty cooling with comparatively less air flow and
heat sinking. The hotter channels may also be located close
to other heat-generating components tending to drive their
temperature even higher. In these cases, the proper
selection of the current sense resistors (R ISEN in Figure 3)
V COMP
+
-
+
-
PWM1
introduces channel current unbalance into the system.
Increasing the value of R ISEN in the cooler channels and
decreasing it in the hotter channels moves all channels into
f(j ω )
SAWTOOTH SIGNAL
thermal balance at the expense of current balance.
I ER
+
-
I AVG
÷ N
Σ
I 4 *
I 3 *
I 2
Voltage Regulation
The output of the error amplifier, V COMP , is compared to the
sawtooth waveform to modulate the pulse width of the PWM
signals. The PWM signals control the timing of the Intersil
MOSFET drivers and regulate the converter output to the
specified reference voltage. Three distinct inputs to the error
I 1
NOTE: *CHANNELS 3 and 4 are OPTIONAL.
FIGURE 4. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
8
amplifier determine the voltage level of V COMP . The internal
and external circuitry which control voltage regulation is
illustrated in Figure 5.
FN9084.8
December 29, 2004
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| ISL6559CB-T | 功能描述:IC REG CTRLR BUCK PWM VM 28-SOIC RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR) |
| ISL6559CBZ | 功能描述:电流型 PWM 控制器 2 TO 4 PHS BUCK CNTRLR 2 8LD RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6559CBZ-T | 功能描述:电流型 PWM 控制器 2 TO 4 PHS BUCK CNTRLR 2 8LD RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6559CR | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR) |
| ISL6559CR-T | 功能描述:IC REG CTRLR BUCK PWM VM 32-QFN RoHS:否 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 标准包装:4,000 系列:- PWM 型:电压模式 输出数:1 频率 - 最大:1.5MHz 占空比:66.7% 电源电压:4.75 V ~ 5.25 V 降压:是 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:无 工作温度:-40°C ~ 85°C 封装/外壳:40-VFQFN 裸露焊盘 包装:带卷 (TR) |
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