参数资料
型号: ISL6559CBZ-T
厂商: Intersil
文件页数: 5/21页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 28-SOIC
标准包装: 1
PWM 型: 电压模式
输出数: 1
频率 - 最大: 4MHz
占空比: 75%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 70°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 标准包装
产品目录页面: 1243 (CN2011-ZH PDF)
其它名称: ISL6559CBZ-TDKR
ISL6559
Electrical Specifications
Operating Conditions: VCC = 5V, T A = 0°C to 70°C. Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ERROR AMPLIFIER
Open-Loop Gain
Open-Loop Bandwidth
Slew Rate
Maximum Output Voltage
Source Current
Sink Current
R L = 10k ? to ground
C L = 100pF, R L = 10k ? to ground
C L = 100pF, Load = ±400mA
R L = 10k ? to ground
-
-
-
3.6
3.0
1.6
72
18
7.1
4.5
7.0
3.0
-
-
11
-
9.5
5.4
dB
MHz
V/ μ s
V
mA
mA
REMOTE-SENSE AMPLIFIER
Input Impedance
Bandwidth
Slew Rate
-
-
-
80
20
6
-
-
-
k ?
MHz
V/ μ s
SENSE CURRENT
IOUT Accuracy
ISEN Offset Voltage
Over-Current Trip Level
ISEN1 = ISEN2 = ISEN3 = ISEN4 = 50 μ A
-5
-
72
-
6
90
5
-
108
%
mV
μ A
POWER GOOD AND PROTECTION MONITORS
PGOOD Low Voltage
Under-Voltage Offset From VID
Over-Voltage Threshold
OVP Voltage
I PGOOD = 4mA
VSEN Falling
VSEN Rising
I OVP = 100mA, VCC = 5V
-
320
2.08
2.2
-
350
2.13
3.28
0.4
420
2.20
4.0
V
mV
V
V
NOTE:
3. These parts are designed and adjusted for accuracy within the system tolerance
Functional Pin Description
this pin to the gate of an SCR or MOSFET tied across V IN
ISL6559CB (28 LEAD SOIC)
TOP VIEW
ISL6559CR (32 LEAD QFN)
TOP VIEW
and ground to prevent damage to a load device.
VID4, VID3, VID2, VID1, VID0
GND 1
28 EN
The state of these five inputs program the internal DAC,
OVP 2
VID4 3
VID3 4
VID2 5
VID1 6
VID0 7
OFS 8
COMP 9
FB 10
IOUT 11
VDIFF 12
27 FS/DIS
26 PGOOD
25 PWM4
24 ISEN4
23 ISEN1
22 PWM1
21 PWM2
20 GND
19 ISEN2
18 ISEN3
17 PWM3
VID2 1
VID1 2
VID0 3
NC 4
OFS 5
COMP 6
FB 7
NC 8
32 31 30 29 28 27 26 25
24 PWM4
23 ISEN4
22 ISEN1
21 PWM1
20 PWM2
19 GND
18 ISEN2
17 ISEN3
9 10 11 12 13 14 15 16
which provides the reference voltage for output regulation.
Connect these pins to either open-drain or active pull-up
type outputs. Pulling these pins above 2.9V can cause a
reference offset inaccuracy.
OFS
Connecting a resistor between this pin and ground creates a
positive offset voltage which is added to the DAC voltage,
allowing easy implementation of load-line regulation. For no
offset, simply tie this pin to ground.
VSEN 13
16 VCC
RGND 14
15 GND
FB and COMP
NC = NO CONNECT
GND
Bias and reference ground for the IC.
OVP
Over-voltage protection pin. This pin pulls to VCC and is
latched when an over-voltage condition is detected. Connect
5
The internal error amplifier inverting input and output
respectively. Connect the external R-C feedback
compensation network of the regulator to these pins.
IOUT
The current carried out of this pin is proportional to output
current and can be used to incorporate output voltage droop
FN9084.8
December 29, 2004
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